Ring-buffer based buffering apparatus and method of using memory apparatus

• US 7,415,592 B2
• Filed: 12/01/2005
• Issued: 08/19/2008
• Est. Priority Date: 12/03/2004
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Sasaki, Dai, Kurosaki, Toshiyuki
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US11/291,489
• Publication Number:
  US 20060140204A1
• Time in Patent Office: 992 Days
• Field of Search: None
• US Class Current: 711/173
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence

Abstract

In a buffering apparatus for digital data for temporarily storing input data and then outputting, a memory apparatus is provided with a plurality of storage areas assigned consecutive identification numbers. A partition designation unit generates an instruction for partitioning the plurality of storage areas. An area partitioning unit partitions the plurality of storage areas in the memory apparatus at least into a first area and a second area in accordance with the generated instruction for partitioning and uses the first area as a buffer area, the first area including storage areas with consecutive identification numbers. A partition designation unit generates an instruction for partitioning that designates a border between the first area and the second area.

Claims

1. A buffering apparatus for digital data that temporarily stores input data and then outputs the data, comprising:

a memory apparatus provided with a plurality of storage areas assigned consecutive identification numbers; and

an area partitioning unit which partitions the plurality of storage areas in the memory apparatus at least into a first area and a second area, and which uses the first area as a ring buffer area, the first area including storage areas with consecutive identification numbers, wherein

digital data is buffered in the first area when a predetermined bit included in a read request is off, and the digital data is buffered in the second area when the predetermined bit is on.

2. The buffering apparatus according to claim 1, further comprising a partition designation unit which generates an instruction for partitioning the plurality of storage areas, wherein

the area partitioning unit partitions the plurality of storage areas in the memory apparatus in accordance with the generated instruction for partitioning.

3. The buffering apparatus according to claim 2, wherein the partition designation unit generates the instruction for partition that designates a border between the first area and the second area.

4. The buffering apparatus according to claim 1, wherein

the first area is used for storing sequential data read from a recording medium and the second area is used for storing data supplied from a central processing unit which controls the memory apparatus, the central processing unit generates the read request including the predetermined bit.

5. The buffering apparatus according to claim 4, wherein

the predetermined bit is used for designating the first area or the second area in which digital data is to be buffered.

6. The buffering apparatus according to claim 4, further comprising a read unit which reads digital data from the recording medium and writes it in the first area or the second area in accordance with the predetermined bit included in the read request.

7. A method of using a memory apparatus provided with a plurality of storage areas assigned consecutive identification numbers, comprising the steps of:

generating an instruction for partitioning the plurality of storage areas; and

partitioning the plurality of storage areas in the memory apparatus at least into a first area and a second area in accordance with the generated instruction for partitioning, and using the first area as a ring buffer area, the first area including storage areas with consecutive identification numbers, wherein

digital data is buffered in the first area when a predetermined bit included in a read request is off, and the digital data is buffered in the second area when the predetermined bit is on.

8. The method of using the memory apparatus according to claim 7, wherein the instruction designates a border between the first area and the second area.

9. The method of using the memory apparatus according to claim 7, wherein:

the first area is used for storing sequential data read from a recording medium and the second area is used for storing data supplied from a central processing unit which controls the memory apparatus, the central processing unit generates the read request including the predetermined bit.

10. The method of using the memory apparatus according to claim 9, wherein:

the predetermined bit is used for designating the first area or the second area in which digital data is to be buffered.

11. The method of using the memory apparatus according to claim 9, further comprising the steps of:

reading digital data from the recording medium; and

writing the digital data in the first area or the second area in accordance with the predetermined bit included in the read request.