Method of fabricating trench MIS device with thick oxide layer in bottom of trench

• US 7,416,947 B2
• Filed: 01/19/2006
• Issued: 08/26/2008
• Est. Priority Date: 07/03/2001
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N.
• Primary Examiner(s): Smith; Zandra V.
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US11/335,747
• Publication Number:
  US 20060121676A1
• Time in Patent Office: 950 Days
• Field of Search: 438/259, 438/268, 438/270, 438/424, 438/430, 438/443, 438/445
• US Class Current: 438/270
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectric layer, which reduces the capacitance between the drain and gate of the device, can be formed in both the active areas of the device, where the switching function is performed, and in the inactive areas where, among other things, contacts are made to the gate electrode.

Claims

1. A method of fabricating an MIS device comprising:

providing a semiconductor substrate;

forming a trench in said substrate;

depositing a mask layer in said trench;

etching said mask layer to form an exposed area at a bottom of said trench;

forming an insulating layer in said exposed area by means of a process comprising chemical vapor deposition;

depositing a conductive material into said trench over the insulating layer; and

creating a contact between said conductive material and a metal layer overlying said substrate.

2. The method of claim 1 wherein forming an insulating layer in said exposed area comprises depositing an insulating layer by chemical vapor deposition such that the insulating layer fills the entire remaining space within the trench and then etching the insulating layer back such that a top surface of the insulating layer is located within the trench.

3. The method of claim 2 wherein depositing said insulating layer by chemical vapor deposition comprises depositing said insulating layer such that said insulating layer overflows a top surface of said substrate.

4. The method of claim 1 wherein said trench is located in a gate bus region of said device.

5. The method of claim 1 wherein said trench is located in a termination region of said device.

6. The method of claim 1 wherein depositing a conductive material into said trench comprises depositing doped polysilicon in said trench.

7. The method of claim 1 wherein depositing a mask layer comprises depositing silicon nitride.

8. The method of claim 1 wherein said substrate comprises silicon.

9. The method of claim 1 wherein said insulating layer comprises an oxide.

10. The method of claim 1 wherein said insulating layer comprises glass.

11. The method of claim 10 wherein said insulating layer comprises phosphosilicate glass.

12. The method of claim 10 wherein said insulating layer comprises borophosphosilicate glass.

13. The method of claim 1 wherein forming a trench comprises etching the substrate and thermally growing a pad oxide.

14. The method of claim 1 wherein forming an insulating layer in said exposed area comprises depositing an insulating layer by chemical vapor deposition such that the insulating layer fills the entire remaining space within the trench and then etching the insulating layer back such that a top surface of the insulating layer is approximately level with a top surface of the substrate.

15. The method of claim 1 comprising removing the mask layer before depositing a conductive material into said trench.

16. The method of claim 15 wherein the substrate is doped with material of a first conductivity type in the vicinity of the trench, the method further comprising:

forming a gate dielectic layer adjoining the insulating layer; and

introducing a dopant of a second conductivity type opposite to the first conductivity type to form a body region such that a PN junction between the body region and a remaining area of the substrate is located near an interface between the gate dielectric layer and the insulating layer.

17. The method of claim 16 wherein introducing a dopant of the second conductivity type comprises diffusing the dopant such that a portion of the PN junction is located below the trench.