Trench FET with improved body to gate alignment

• US 7,416,948 B2
• Filed: 10/23/2006
• Issued: 08/26/2008
• Est. Priority Date: 12/30/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Kraft, Nathan L., Dolny, Gary M., Challa, Ashok, Sapp, Steven P., Yilmaz, Hamza, Calafut, Daniel, Probst, Dean E., Ridley, Rodney S., Grebs, Thomas E., Kocon, Christopher B.
• Primary Examiner(s): Geyer, Scott B.
• Assistant Examiner(s): Lee, Cheung
• Application Number:
  US11/551,992
• Publication Number:
  US 20070082441A1
• Time in Patent Office: 673 Days
• Field of Search: 438/269, 257/E21.147, 257/E21.4, 257/E21.419, 257/E21.615
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.

Claims

1. A method of forming a field effect transistor, comprising:

forming trenches in a semiconductor region of a first conductivity type;

partially filling each trench with one or more materials;

performing a dual-pass angled implant to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material;

performing a high temperature process to drive the implanted dopants deeper into mesa region thereby forming body regions of the second conductivity type between adjacent trenches; and

forming source regions of the first conductivity type in each body region.

2. The method of claim 1 wherein the body region extends deeper near the trenches than in the middle of the mesa region between adjacent trenches.

3. The method of claim 1 wherein the step of partially filling the trenches comprises:

filling the trenches with a dielectric material; and

performing a first dielectric recess to recess the dielectric material to a first depth within each trench.

4. The method of claim 3 further comprising:

after the dual-pass angled implant, performing a second dielectric recess to further recess the dielectric material, wherein a remaining portion of the dielectric material after the second dielectric recess forms a thick bottom dielectric in a bottom portion of each trench.

5. The method of claim 4 wherein the high temperature process comprises forming a gate dielectric layer lining sidewalls of each trench.

6. The method of claim 4 further comprising forming a gate dielectric layer lining sidewalls of each trench, wherein the high temperature process comprises a body drive-in process.

7. The method of claim 4 further comprising:

forming a gate dielectric layer lining sidewalls of each trench;

forming a gate electrode in each trench;

forming source regions of the first conductivity type in the body region; and

forming heavy body regions of the second conductivity type in the body regions, the heavy body regions having a higher doping concentration than the body regions.

8. The method of claim 1 wherein the step of partially filling the trenches comprises:

filling a bottom portion of each trench with a shield electrode, the shield electrodes being insulated from the semiconductor region;

filling a remaining portion of each trench with a dielectric material;

performing a first dielectric recess to recess the dielectric material to a first depth within each trench.

9. The method of claim 8 further comprising:

after the dual-pass angled implant, performing a second dielectric recess to further recess the dielectric material wherein a remaining portion of the dielectric material after the second dielectric recess forms an inter-electrode dielectric layer over the shield electrode in each trench.

10. The method of claim 9 wherein the high temperature process comprises forming a gate dielectric layer lining upper sidewalls of each trench.

11. The method of claim 9 further comprising forming a gate dielectric layer lining upper sidewalls of each trench, wherein the high temperature process comprises a body drive-in process.

12. The method of claim 9 further comprising:

forming a shield dielectric layer lining lower sidewalls of each trench, the shield dielectric layer insulating the shield electrode in each trench from the semiconductor region;

forming a gate dielectric layer lining upper sidewalls of each trench, the gate dielectric layer being thinner than the shield dielectric layer;

forming a gate electrode in an upper portion of each trench, each gate electrode being insulated from its underlying shield electrode;

forming source regions of the first conductivity type in the body region adjacent the trenches; and

forming heavy body regions of the second conductivity type in the body regions, the heavy body regions having a higher doping concentration than the body regions.

13. The method of claim 1 wherein the step of partially filling the trenches comprises:

forming a shield dielectric layer lining sidewalls and bottom of each trench;

filling each trench with a conductive material; and

recessing the conductive material to a first depth within each trench.

14. The method of claim 13 further comprising:

after the dual-pass angled implant, further recessing the conductive material into each trench, a remaining portion of each conductive material forming a shield electrode in each trench.

15. The method of claim 14 further comprising:

prior to performing the dual-pass angled implant, thinning down portions of the shield dielectric layer not covered by the recessed conductive material.

16. The method of claim 14 wherein the high temperature process comprises forming a gate dielectric layer lining upper sidewalls of each trench.

17. The method of claim 14 further comprising forming a gate dielectric layer lining upper sidewalls of each trench, wherein the high temperature process comprises a body drive-in process.

18. The method of claim 14 further comprising:

forming a gate dielectric layer lining upper sidewalls of each trench, the gate dielectric layer being thinner than the shield dielectric layer;

forming a gate electrode in an upper portion of each trench, each gate electrode being insulated from its underlying shield electrode;

forming source regions of the first conductivity type in the body region adjacent the trenches; and

forming heavy body regions of the second conductivity type in the body region, the heavy body regions having a higher doping concentration than the body region.

19. A method of forming a field effect transistor, comprising:

forming trenches in a semiconductor region of a first conductivity type;

filling the trenches with a dielectric material;

recessing the dielectric material to a first depth within each trench;

performing a dual-pass angled implant to implant dopants of a second conductivity type into mesa regions between adjacent trenches through upper trench sidewalls not covered by the recessed dielectric material;

after the dual-pass angled implant, further recessing the recessed dielectric material; and

performing a high temperature process to drive the implanted dopants deeper into the mesa region to thereby form a body region of the second conductivity type in the semiconductor region.

20. The method of claim 19 wherein a remaining portion of the dielectric material after the second dielectric recess forms a thick bottom dielectric in a bottom portion of each trench.

21. The method of claim 19 wherein the high temperature process comprises forming a gate dielectric layer lining sidewalls of each trench.

22. The method of claim 19 further comprising forming a gate dielectric layer lining sidewalls of each trench, wherein the high temperature process comprises a body drive-in process.

23. The method of claim 19 further comprising:

forming a gate dielectric layer lining sidewalls of each trench; and

forming a gate electrode in each trench.

24. The method of claim 19 further comprising:

forming source regions of the first conductivity type in the body region;

forming heavy body regions of the second conductivity type in the body region, the heavy body regions having a higher doping concentration than the body region.

25. The method of claim 19 wherein the body region extends deeper near the trenches than in the middle of the mesa region between adjacent trenches.

26. The method of claim 19 wherein the semiconductor includes a substrate and an epitaxial layer extending over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the trenches extending into and terminating within the epitaxial layer.

27. A method of forming a shielded gate field effect transistor, comprising:

forming trenches in a semiconductor region of a first conductivity type;

filling a bottom portion of each trench with a shield electrode, the shield electrodes being insulated from the semiconductor region;

filling a remaining portion of each trench with a dielectric material;

recessing the dielectric material to a first depth within each trench;

performing a dual-pass angled implant to implant dopants of a second conductivity type into mesa regions between adjacent trenches through upper trench sidewalls not covered by the recessed dielectric material;

after the dual-pass angled implant, further recessing the recessed dielectric material; and

performing a high temperature process to drive the implanted dopants deeper into the mesa region to thereby form a body region of the second conductivity type in the semiconductor region.

28. The method of claim 27 wherein a remaining portion of the dielectric material after the two recessing steps forms an inter-electrode dielectric layer over the shield electrode in each trench.

29. The method of claim 27 wherein the high temperature process comprises forming a gate dielectric layer lining upper sidewalls of each trench.

30. The method of claim 27 further comprising forming a gate dielectric layer lining upper sidewalls of each trench, wherein the high temperature process comprises a body drive-in process.

31. The method of claim 27 further comprising:

forming a shield dielectric layer lining lower sidewalls of each trench, the shield dielectric layer insulating the shield electrode in each trench from the semiconductor region;

forming a gate dielectric layer lining upper sidewalls of each trench, the gate dielectric layer being thinner than the shield dielectric layer; and

forming a gate electrode in each trench in an upper portion of each trench, each gate electrode being insulated from its underlying shield electrode.

32. The method of claim 27 further comprising:

forming source regions of the first conductivity type in the body region adjacent the trenches;

forming heavy body regions of the second conductivity type in the body region, the heavy body regions having a higher doping concentration than the body region.

33. The method of claim 27 wherein the body region extends deeper near the trenches than in the middle of the mesa region between adjacent trenches.

34. The method of claim 27 wherein the semiconductor includes a substrate and an epitaxial layer extending over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the trenches extending into and terminating within the epitaxial layer.

35. The method of claim 27 wherein the semiconductor includes a substrate and an epitaxial layer extending over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the trenches extending through the epitaxial layer and terminating within the substrate.

36. A method of forming a shielded gate field effect transistor, comprising:

forming trenches in a semiconductor region of a first conductivity type;

forming a shield dielectric layer lining sidewalls and bottom of each trench;

filling each trench with a conductive material;

recessing the conductive material to a first depth within each trench;

performing a dual-pass angled implant to implant dopants of a second conductivity type into mesa regions between adjacent trenches through upper trench sidewalls not covered by the recessed conductive material;

after the dual-pass angled implant, further recessing the conductive material into each trench, a remaining portion of each conductive material forming a shield electrode in each trench; and

performing a high temperature process to drive the implanted dopants deeper into the mesa region to thereby form a body region of the second conductivity type in the semiconductor region.

37. The method of claim 36 further comprising:

prior to performing the dual-pass angled implant, thinning down portions of the shield dielectric layer not covered by the recessed conductive material.

38. The method of claim 36 wherein the high temperature process comprises forming a gate dielectric layer lining upper sidewalls of each trench.

39. The method of claim 36 further comprising forming a gate dielectric layer lining upper sidewalls of each trench, wherein the high temperature process comprises a body drive-in process.

40. The method of claim 36 further comprising:

forming a gate dielectric layer lining upper sidewalls of each trench, the gate dielectric layer being thinner than the shield dielectric layer; and

forming a gate electrode in each trench in an upper portion of each trench, each gate electrode being insulated from its underlying shield electrode.

41. The method of claim 36 further comprising:

forming source regions of the first conductivity type in the body region adjacent the trenches;

forming heavy body regions of the second conductivity type in the body region, the heavy body regions having a higher doping concentration than the body region.

42. The method of claim 36 wherein the body region extends deeper near the trenches than in the middle of the mesa region between adjacent trenches.

43. The method of claim 36 wherein the semiconductor includes a substrate and an epitaxial layer extending over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the trenches extending into and terminating within the epitaxial layer.

44. The method of claim 36 wherein the semiconductor includes a substrate and an epitaxial layer extending over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the trenches extending through the epitaxial layer and terminating within the substrate.