Top layers of metal for integrated circuits

• US 7,416,971 B2
• Filed: 09/23/2004
• Issued: 08/26/2008
• Est. Priority Date: 09/23/2004
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming
• Primary Examiner(s): Vu; David
• Assistant Examiner(s): Nguyen; Thinh T
• Application Number:
  US10/948,020
• Publication Number:
  US 20060063371A1
• Time in Patent Office: 1,433 Days
• Field of Search: 438/618, 438/587, 438/629, 438/654, 438/201, 438/211, 438/257, 257/314, 257/315, 257/398
• US Class Current: 438/618
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

Claims

1. A method for fabricating a chip comprising:

providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, and a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said first metallization structure and exposes said contact point;

forming a second metallization structure over said contact point and over said passivation layer, wherein said second metallization structure is connected to said contact point through said first opening, and wherein said forming said second metallization structure comprises sputtering a first adhesion layer over said contact point and over said passivation layer, sputtering a first seed layer over said first adhesion layer, forming a first photoresist layer on said first seed layer, wherein a second opening in said first photoresist layer exposes said first seed layer, electroplating a first bulk metal layer on said first seed layer exposed by said second opening, removing said first photoresist layer, and removing said first seed layer and said first adhesion layer not under said first bulk metal layer;

forming a polymer layer on said second metallization structure and over said passivation layer;

polishing said polymer layer; and

after said polishing said polymer layer, forming a third metallization structure on said polymer layer, wherein said forming said third metallization structure comprises sputtering a second adhesion layer over said polymer layer, sputtering a second seed layer over said second adhesion layer, forming a second photoresist layer on said second seed layer, wherein a third opening in said second photoresist layer exposes said second seed layer, electroplating a second bulk metal layer on said second seed layer exposed by said third opening, removing said second photoresist layer, and removing said second seed layer and said second adhesion layer not under said second bulk metal layer.

2. The method of claim 1, wherein said sputtering said first seed layer comprises sputtering a copper layer with a thickness between 0.05 and 3 micrometers on said first adhesion layer.

3. The method of claim 1, wherein said sputtering said first seed layer comprises sputtering a gold layer with a thickness between 0.05 and 3 micrometers on said first adhesion layer.

4. The method of claim 1, wherein said electroplating said first bulk metal layer comprises electroplating a gold layer with a thickness between 2 and 100 micrometers on said first seed layer exposed by said second opening.

5. The method of claim 1, wherein said electroplating said first bulk metal layer comprises electroplating a copper layer with a thickness between 2 and 100 micrometers on said first seed layer exposed by said second opening.

6. The method of claim 1, wherein said third metallization structure comprises a connection to an external circuit though a solder bump.

7. The method of claim 1, wherein said third metallization structure comprises a connection to an external circuit through a wirebond.

8. The method of claim 1, after said forming said polymer layer, further comprising forming a fourth opening in said polymer layer exposing said second metallization structure, followed by said polishing said polymer layer, followed by said forming said third metallization structure connected to said second metallization structure through said fourth opening.

9. The method of claim 1, wherein said forming said polymer layer comprises forming a polyimide layer on said second metallization structure and over said passivation layer.

10. The method of claim 1, wherein said forming said polymer layer comprises forming a benzocyclobutene (BCB) layer on said second metallization structure and over said passivation layer.

11. The method of claim 1, wherein said sputtering said first adhesion layer comprises sputtering a titanium-containing layer with a thickness between 0.03 and 2 micrometers over said contact point and over said passivation layer.

12. The method of claim 1, wherein said sputtering said second adhesion layer comprises sputtering a titanium-containing layer with a thickness between 0.03 and 2 micrometers over said polymer layer.

13. The method of claim 1, wherein said electroplating said second bulk metal layer comprises electroplating a copper layer with a thickness between 2 and 100 micrometers on said second seed layer exposed by said third opening.

14. The method of claim 1, wherein said electroplating said second bulk metal layer comprises electroplating a gold layer with a thickness between 2 and 100 micrometers on said second seed layer exposed by said third opening.

15. The method of claim 1, wherein said forming said first photoresist layer and said forming said second photoresist layer comprises using a 1×

stepper.

16. The method of claim 1, wherein said sputtering said second seed layer comprises sputtering a gold layer with a thickness between 0.05 and 3 micrometers on said second adhesion layer.

17. The method of claim 1, wherein said sputtering said second seed layer comprises sputtering a copper layer with a thickness between 0.05 and 3 micrometers on said second adhesion layer.

18. The method of claim 1, wherein said polishing said polymer layer comprises chemical-mechanical polishing.