Semiconductor device having internal stress film

• US 7,417,289 B2
• Filed: 04/05/2007
• Issued: 08/26/2008
• Est. Priority Date: 06/16/2003
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tsutsui, Masafumi, Akamatsu, Kaori, Umimoto, Hiroyuki
• Primary Examiner(s): Weiss; Howard
• Application Number:
  US11/730,988
• Publication Number:
  US 20070194388A1
• Time in Patent Office: 509 Days
• Field of Search: 257/369
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

Claims

1. A semiconductor device, comprising a MISFET, wherein the MISFET includes:

an active region made of a semiconductor substrate;

a gate insulating film formed on the active region;

a gate electrode formed on the gate insulating film;

source/drain regions formed in regions of the active region located on both sides of the gate electrode; and

an internal stress film formed on the source/drain regions and for generating a stress in a gate length direction in a channel region located in the active region under the gate electrode, and the internal stress film is not formed on an upper surface of the gate electrode.

2. The semiconductor device of claim 1, wherein the internal stress film is for generating the stress in a substantially parallel direction to the gate length direction.

3. The semiconductor device of claim 2, wherein the substantially parallel direction of the stress includes a direction tilted by an angle of less than 10 degree from a direction which carriers move.

4. The semiconductor device of claim 1, wherein the internal stress film is directly in contact with the source/drain regions.

5. The semiconductor device of claim 1, wherein the internal stress film is formed above the source/drain regions with a thin film interposed therebetween.

6. The semiconductor device of claim 1, wherein the internal stress film includes multiple layers.

7. The semiconductor device of claim 1, wherein the source/drain regions include a lightly doped impurity region, a heavily doped impurity region and a suicide layer.

8. The semiconductor device of claim 1, further comprising a sidewall formed on a side surface of the gate electrode.

9. The semiconductor device of claim 1, wherein the internal stress film is in contact with a side surface of the gate electrode.

10. The semiconductor device of claim 1, wherein a principal surface of the semiconductor substrate is substantially a {100} plane, and the gate length direction of the gate electrode is substantially a <

011>

direction.

11. The semiconductor device of claim 1, further comprising:

an interlevel insulating film formed on the internal stress film; and

a contact plug provided so as to pass through the interlevel insulating film and the internal stress film and to be connected to the source/drain regions.

12. The semiconductor device of claim 1, wherein the active region is divided by an isolation region formed in the semiconductor substrate.

13. The semiconductor device of claim 1, wherein the gate insulating film is a silicon oxide film.

14. The semiconductor device of claim 1, wherein the gate insulating film is a silicon oxynitride film.

15. The semiconductor device of claim 1, wherein the gate electrode has a polysilicon film.

16. The semiconductor device of claim 1, wherein the gate electrode has a metal film.

17. The semiconductor device of claim 1, wherein the internal stress film is provided so as to cover at least part of at least one of the source/drain regions.

18. The semiconductor device of claim 1, wherein the internal stress film covers at least respective parts of the source/drain regions.

19. The semiconductor device of claim 1, wherein the internal stress film covers respective parts of both side surfaces of the gate electrode.

20. The semiconductor device of claim 1, wherein the MISFET is an nMISFET, the source/drain regions is n-type source/drain regions, and the internal stress film generates a tensile stress.

21. The semiconductor device of claim 20, wherein the internal stress film is for generating the tensile stress in a substantially parallel direction to the gate length direction.

22. The semiconductor device of claim 20, wherein the substantially parallel direction of the tensile stress includes a direction tilted by an angle of less than 10 degrees from a direction in which electrons move.

23. The semiconductor device of claim 20, wherein the internal stress film is made of a silicon nitride film.

24. The semiconductor device of claim 20, wherein the n-type source/drain regions includes an n-type lightly doped impurity region, an n-type heavily doped impurity region and a silicide layer.

25. The semiconductor device of claim 1, wherein the MISFET is an pMISFET, the source/drain regions is p-type source/drain regions, and the internal stress film generates a compressive stress.

26. The semiconductor device of claim 25, wherein the internal stress film is for generating the compressive stress in a substantially parallel direction to the gate length direction.

27. The semiconductor device of claim 25, wherein the substantially parallel direction of the compressive stress includes a direction tilted by an angle of less than 10 degrees from a direction in which holes move.

28. The semiconductor device of claim 25, wherein the internal stress film is made of a TEOS film.

29. The semiconductor device of claim 25, wherein the p-type source/drain regions includes a p-type lightly doped impurity region, a p-type heavily doped impurity region and a silicide layer.