Post passivation interconnection schemes on top of the IC chips

• US 7,417,317 B2
• Filed: 06/13/2007
• Issued: 08/26/2008
• Est. Priority Date: 10/15/2003
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming
• Primary Examiner(s): Picardat; Kevin M
• Application Number:
  US11/818,028
• Publication Number:
  US 20070246834A1
• Time in Patent Office: 440 Days
• Field of Search: 257/690, 257/700, 257/691, 257/920, 257/773, 257/774, 438614-616, 438/622, 438/631, 438/637, 438/638
• US Class Current: 257/773
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A chip structure comprising:

a silicon substrate;

a first I/O circuit in or on said silicon substrate, wherein said first I/O circuit comprises a first receiver;

a second I/O circuit in or on said silicon substrate;

a first ESD circuit in or on said silicon substrate;

a dielectric layer over said silicon substrate;

a first metallization structure over said silicon substrate and in said dielectric layer, wherein said first metallization structure comprises a first interconnecting structure over said silicon substrate and in said dielectric layer, a second interconnecting structure over said silicon substrate and in said dielectric layer, and a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first ESD circuit, wherein said second interconnecting structure is connected to said first I/O circuit, and wherein said third interconnecting structure is connected to said second I/O circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers; and

a second metallization structure over said passivation layer, wherein said first ESD circuit is connected to said first and second I/O circuits through said second metallization structure, wherein said first ESD circuit is connected to said first I/O circuit through, in sequence, said first interconnecting structure, said second metallization structure and said second interconnecting structure, and wherein said first ESD circuit is connected to said second I/O circuit through, in sequence, said first interconnecting structure, said second metallization structure and said third interconnecting structure.

2. The chip structure of claim 1 further comprising a second ESD circuit in or on said silicon substrate, wherein said second ESD circuit is connected to said first and second I/O circuits and to said first ESD circuit through said second metallization structure.

3. The chip structure of claim 1, wherein said second I/O circuit comprises a driver.

4. The chip structure of claim 1, wherein said second I/O circuit comprises a second receiver.

5. The chip structure of claim 1, wherein said nitride layer comprises silicon nitride.

6. The chip structure of claim 1, wherein said nitride layer comprises oxynitride.

7. The chip structure of claim 1, wherein said second metallization structure comprises electroplated gold.

8. The chip structure of claim 1, wherein said second metallization structure comprises electroplated copper.

9. The chip structure of claim 1, wherein said second metallization structure comprises electroplated silver.

10. The chip structure of claim 1, wherein said second metallization structure comprises electroplated palladium.

11. The chip structure of claim 1, wherein said second metallization structure comprises electroplated nickel.

12. The chip structure of claim 1, wherein metal in said second metallization structure has a thickness greater than 2 micrometers.

13. A chip structure comprising:

a silicon substrate;

a first I/O circuit in or on said silicon substrate;

a second I/O circuit in or on said silicon substrate;

a dielectric layer over said silicon substrate;

a first metallization structure over said silicon substrate and in said dielectric layer, wherein said first metallization structure is connected to said first I/O circuit;

a second metallization structure over said silicon substrate and in said dielectric layer, wherein said second metallization structure is connected to said second I/O circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers;

a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness greater than that of said passivation layer, and wherein said first polymer layer has a thickness between 2 and 150 micrometers;

a third metallization structure over said first polymer layer, wherein said third metallization structure connects said first and second metallization structures, wherein said first I/O circuit is connected to said second I/O circuit through, in sequence, said first metallization structure, said third metallization structure and said second metallization structure, and wherein a signal stimuli is provided to said first and second I/O circuits through said third metallization structure; and

a second polymer layer on said third metallization structure, wherein said second polymer layer has a thickness between 2 and 150 micrometers.

14. The chip structure of claim 13, wherein said first polymer layer comprises polyimide.

15. The chip structure of claim 13, wherein said first I/O circuit comprises a receiver.

16. The circuit component of claim 13, wherein said nitride layer comprises silicon nitride.

17. The chip structure of claim 13, wherein said nitride layer comprises oxynitride.

18. The chip structure of claim 13, wherein said third metallization structure comprises electroplated gold.

19. The chip structure of claim 13, wherein said third metallization structure comprises electroplated copper.

20. The chip structure of claim 13, wherein said third metallization structure comprises electroplated silver.

21. The chip structure of claim 13, wherein said third metallization structure comprises electroplated palladium.

22. The chip structure of claim 13, wherein said third metallization structure comprises electroplated nickel.

23. The chip structure of claim 13, wherein metal in said third metallization structure has a thickness greater than 2 micrometers.

24. The chip structure of claim 13 further comprising an ESD circuit in or on said silicon substrate, wherein said ESD circuit is connected to said first and second I/O circuits through said third metallization structure.

25. A chip structure comprising:

a silicon substrate;

a first internal circuit in or on said silicon substrate, wherein said first internal circuit comprises a first signal node;

a second internal circuit in or on said silicon substrate, wherein said second internal circuit comprises a second signal node;

a dielectric layer over said silicon substrate;

a first metallization structure over said silicon substrate and in said dielectric layer, wherein said first metallization structure comprises a first interconnecting structure over said silicon substrate and in said dielectric layer, and a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first signal node, and wherein said second interconnecting structure is connected to said second signal node;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers;

a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness greater than that of said passivation layer, and wherein said first polymer layer has a thickness between 2 and 150 micrometers;

a second metallization structure over said first polymer layer, wherein said second metallization structure connects said first and second signal nodes, wherein said first signal node is connected to said second signal node through, in sequence, said first interconnecting structure, said second metallization structure and said second interconnecting structure, and wherein a first product of resistance of a first portion of said second metallization structure times capacitance of said first portion is at least 100 times less than a second product of resistance of a second portion of said first metallization structure times capacitance of said second portion wherein said first portion has a same length as said second portion; and

a second polymer layer on said second metallization structure, wherein said second polymer layer has a thickness between 2 and 150 micrometers.

26. The circuit component of claim 25, wherein said nitride layer comprises silicon nitride.

27. The chip structure of claim 25, wherein said nitride layer comprises oxynitride layer.

28. The chip structure of claim 25, wherein said second metallization structure comprises electroplated gold.

29. The chip structure of claim 25, wherein said second metallization structure comprises electroplated copper.

30. The chip structure of claim 25, wherein said second metallization structure comprises electroplated silver.

31. The chip structure of claim 25, wherein said second metallization structure comprises electroplated palladium.

32. The chip structure of claim 25, wherein said second metallization structure comprises electroplated nickel.

33. The chip structure of claim 25, wherein metal in said second metallization structure has a thickness greater than 2 micrometers.

34. The chip structure of claim 25 further comprising an ESD circuit in or on said silicon substrate, wherein said ESD circuit is connected to said first and second internal circuits through said second metallization structure.

35. The chip structure of claim 25 further comprising an I/O circuit in or on said silicon substrate, wherein said I/O circuit is connected to said first and second internal circuits through said second metallization structure.

36. The chip structure of claim 35, wherein said I/O circuit comprises a driver.

37. The chip structure of claim 35, wherein said I/O circuit comprises a receiver.

38. The chip structure of claim 25, wherein said first product is at least 1000 times less than said second product.