System-in-package structure

• US 7,417,329 B2
• Filed: 05/25/2006
• Issued: 08/26/2008
• Est. Priority Date: 12/14/2005
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chu, Chi-Chih, Lee, Cheng-Yin, Chuang, Meng-Jung, Tai, Wei-Chang
• Primary Examiner(s): CLARK, SHEILA V
• Application Number:
  US11/420,230
• Publication Number:
  US 20070132093A1
• Time in Patent Office: 824 Days
• Field of Search: 257/786, 257/784, 257/778, 257/780, 257/781, 257/787, 257/698, 257/700
• US Class Current: 257/786
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 2203/0588 : Second resist used as pattern over first resist
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: H05K 3/3452 : Solder masks

Abstract

A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.

Claims

1. A system-in-package structure, comprising:

a carrier substrate, wherein the surface of the carrier substrate defines a molding area having a contact surface and a periphery area;

a chip disposed in the molding area;

a molding compound disposed in the molding area and covering the chip;

a plurality of solder pads disposed on the surface of the carrier substrate and in the periphery area; and

a solder mask disposed on the periphery area and partially exposing the surface of the solder pads, wherein the solder mask comprises at least one void, wherein the height of the solder pads is higher than the contact surface of the molding area and thereby preventing the molding compound from flooding out of the molding area.

2. The system-in-package structure of claim 1, wherein the chip is a flip chip.

3. The system-in-package structure of claim 1 further comprising a plurality of wires connecting the chip and the carrier substrate, wherein the wires are covered by the molding compound.

4. The system-in-package structure of claim 1 further comprising a plurality of solder balls disposed on the bottom surface of the carrier substrate.

5. The system-in-package structure of claim 1, wherein the depth of the molding area is greater than the depth of the periphery area.

6. The system-in-package structure of claim 1, wherein the molding compound and the carrier substrate comprise a contacting surface, the contacting surface is lower than the solder mask, and the tip of an opening above the solder pads.

7. A system-in-package structure, comprising:

a bottom package structure, comprising;

a first carrier substrate, wherein the surface of the first carrier substrate defines a molding area and a periphery area;

a first chip disposed in the molding area;

a first molding compound disposed in the molding area and covering the first chip;

a plurality of solder pads disposed on the surface of the first carrier substrate and in the periphery area; and

a solder mask disposed on the periphery area and partially exposing the surface of the solder pads, wherein the solder mask comprises at least one void providing a containment area for mold overflow;

a top package structure, comprising;

a second carrier substrate;

a second chip disposed on the surface of the second carrier substrate;

a second molding compound covering the second chip; and

a plurality of solder balls bonding to the upper surface of the first carrier substrate and the bottom surface of the second carrier substrate.

8. The system-in-package structure of claim 7, wherein the first chip and the second chip are flip chips.

9. The system-in-package structure of claim 7, wherein the bottom package structure further comprises a plurality of wires connecting the first chip and the first carrier substrate, wherein the wires are covered by the first molding compound.

10. The system-in-package structure of claim 7, wherein the top package structure further comprises a plurality of wires connecting the second chip and the second carrier substrate, wherein the wires are covered by the second molding compound.

11. The system-in-package structure of claim 7, wherein the bottom package structure comprises a plurality of solder balls disposed on the bottom surface of the first carrier substrate.

12. The system-in-package structure of claim 7, wherein the depth of the molding area is greater than the depth of the periphery area.

13. The system-in-package structure of claim 7, wherein the surface of the solder pads is higher than or equal to the surface of the molding area.

14. The system-in-package structure of claim 7, wherein the surface of the solder pads is higher than or equal to the surface of the solder mask.

15. The system-in-package structure of claim 7 further comprising a third carrier substrate, wherein the third carrier substrate connects the bottom packages structure and the top package structure through the solder balls.

16. The system-in-package structure of claim 7, wherein the first molding compound and the first carrier substrate comprise a contacting surface, the contacting surface is lower than the solder mask, and the tip of an opening above the solder pads.

17. A system-in-package structure, comprising:

a carrier substrate, wherein the surface of the carrier substrate defines a molding area having a contact surface and a periphery area;

a chip disposed in the molding area;

a molding compound disposed in the molding area and covering the chip;

a plurality of solder pads disposed on the surface of the carrier substrate and in the periphery area; and

a solder mask disposed on the periphery area and partially exposing the surface of the solder pads, wherein the solder mask comprises at least one void and the height of the solder pads is greater than the height of the solder mask and thereby preventing the molding compound from flooding out of the molding area.