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Wafer stage storage structure speed testing

  • US 7,417,449 B1
  • Filed: 11/15/2005
  • Issued: 08/26/2008
  • Est. Priority Date: 11/15/2005
  • Status: Expired due to Fees
First Claim
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1. A test integrated circuit manufactured on a semiconductor wafer, the test integrated circuit comprising:

  • a test storage structure; and

    an access controller coupled to the test storage structure and configured to access the test storage structure;

    wherein the access controller comprises a clock source comprising a pulse width generator configured to independently generate a clock signal for accessing the test storage structure;

    wherein the pulse width generator is configured to be programmable and configured to generate the clock signal as a pulse train at a number of frequencies;

    wherein the access controller is configured to internally store within one or more registers, test results of testing of the test storage structure; and

    wherein the one or more registers are accessible by automated test equipment configured to interpret the test results and to indicate functionality of another storage structure within another integrated circuit manufactured on the same semiconductor wafer as the test integrated circuit.

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