Wafer stage storage structure speed testing

• US 7,417,449 B1
• Filed: 11/15/2005
• Issued: 08/26/2008
• Est. Priority Date: 11/15/2005
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Posey, Randal L., Ciraula, Michael K.
• Primary Examiner(s): Nguyen; Ha
• Assistant Examiner(s): ISLA RODAS, RICHARD
• Application Number:
  US11/274,595
• Time in Patent Office: 1,015 Days
• Field of Search: None
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]

Abstract

A system for testing integrated circuit storage structures on a semiconductor wafer. A test IC manufactured on a semiconductor wafer includes a test storage structure such as a random access memory structure, for example, and an access controller including one or more clock sources. In various embodiments, the clock sources may include a ring oscillator and a pulse width generator. These clock sources may be programmable to provide a clock signal having a variety of frequencies for accessing the storage structure. In one embodiment, the frequencies provided by the access controller may be higher than a frequency that can be supplied to the wafer from ATE. In another embodiment, the pulse width generator may be programmable to provide a pulse train having a variety of duty cycles.

Claims

1. A test integrated circuit manufactured on a semiconductor wafer, the test integrated circuit comprising:

a test storage structure; and

an access controller coupled to the test storage structure and configured to access the test storage structure;

wherein the access controller comprises a clock source comprising a pulse width generator configured to independently generate a clock signal for accessing the test storage structure;

wherein the pulse width generator is configured to be programmable and configured to generate the clock signal as a pulse train at a number of frequencies;

wherein the access controller is configured to internally store within one or more registers, test results of testing of the test storage structure; and

wherein the one or more registers are accessible by automated test equipment configured to interpret the test results and to indicate functionality of another storage structure within another integrated circuit manufactured on the same semiconductor wafer as the test integrated circuit.

2. The test integrated circuit as recited in claim 1, wherein each of said number of given frequencies is higher than any frequency supplied by automated test equipment (ATE).

3. The test integrated circuit as recited in claim 1, wherein the pulse width generator is programmable and configured to generate the clock signal as a pulse train having a number of duty cycles.

4. The test integrated circuit as recited in claim 1, wherein the access controller is further configured to provide address and data signals for reading and writing the test storage structure in response to receiving one or more signals from automated test equipment.

5. The test integrated circuit as recited in claim 4, wherein the automated test equipment is configured to indicate functionality of other storage structures within other integrated circuits manufactured on the same semiconductor wafer based on the results from the reading and writing the test storage structure.

6. The test integrated circuit as recited in claim 5, wherein the test integrated circuit is formed in a location on the semiconductor wafer normally designated for one of the other integrated circuits.

7. The test integrated circuit as recited in claim 1, wherein the test integrated circuit is formed on the semiconductor wafer within one or more scribe lanes.

8. The test integrated circuit as recited in claim 1, wherein the test storage structure comprises a test random access memory (RAM) structure.

10. The test integrated circuit as recited in claim 1, wherein the test storage structure comprises a test read only memory structure.

9. A test integrated circuit manufactured on a semiconductor wafer, the test integrated circuit comprising:

a test storage structure comprising a test register file structure; and

an access controller coupled to the test storage structure and configured to access the test storage structure;

wherein the access controller comprises a clock source configured to independently generate a clock signal for accessing the test storage structure;

wherein the clock source is configured to programmably generate the clock signal at a number of frequencies;

wherein the access controller is configured to internally store within one or more registers, test results of testing of the test storage structure; and

wherein the one or more registers are accessible by automated test equipment configured to interpret the test results and to indicate functionality of another storage structure within another integrated circuit manufactured on the same semiconductor wafer as the test integrated circuit.

11. A method comprising:

forming a test integrated circuit on a semiconductor wafer, wherein the test IC includes;

a test storage structure;

an access controller coupled to the test storage structure, wherein the access controller includes a clock source; and

the access controller independently generating a clock signal to access the test storage structure;

programmably generating the clock signal at a number of frequencies; and

interpreting results of said accessing to indicate functionality of another storage structure within another integrated circuit manufactured on the same semiconductor wafer as the test integrated circuit.

12. The method as recited in claim 11, wherein each of said number of frequencies is higher than any frequency supplied by ATE.

13. The method as recited in claim 11, further comprising accessing data from the test storage structure in response to a signal provided by external automated test equipment.

14. The method as recited in claim 11, wherein the test storage structure comprises a test random access memory (RAM) structure.

15. A test system, comprising:

automated test equipment; and

a semiconductor wafer comprising a plurality of integrated circuits including one or more test integrated circuits;

wherein the one or more test integrated circuits are located in positions on the semiconductor wafer normally designated for others of the integrated circuits, and wherein each of the one or more test integrated circuits includes;

a test storage structure; and

an access controller coupled to the test storage structure and configured to access the test storage structure;

wherein the access controller comprises a clock source configured to independently generate a clock signal for accessing the test storage structure; and

wherein the clock source is configured to programmably generate the clock signal at a number of frequencies, each of which is higher than any frequency supplied by the automated test equipment.

16. The test system as recited in claim 15, wherein the test storage structure comprises a test random access memory (RAM) structure.