Method and system for refreshing a memory device during reading thereof

• US 7,417,900 B2
• Filed: 04/02/2007
• Issued: 08/26/2008
• Est. Priority Date: 04/03/2006
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pascucci, Luigi, Rolandi, Paolo
• Primary Examiner(s): Auduong, Gene N.
• Application Number:
  US11/695,552
• Publication Number:
  US 20070279996A1
• Time in Patent Office: 512 Days
• Field of Search: 365/185.25, 365/185.22, 365/185.21, 365/185.2, 365/222, 365/233.5
• US Class Current: 365/185.25
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

A refresh circuit for refreshing a memory device is proposed. The refresh circuit includes: reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells each one having a reference threshold voltage, means for detecting the reaching of a comparison current by a cell current of each memory cell and by a reference current of each reference cell, and means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and the reference currents, and writing means for applying a writing voltage to at least one selected of the memory cells; the refresh circuit further includes control means for enabling the writing means during at least part of the application of the biasing voltage after the determination of the condition of each selected memory cell.

Claims

1. A refresh circuit for refreshing a memory device, the refresh circuit comprising:

reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells, each one of the reference cells having a reference threshold voltage;

means for detecting reaching of a comparison current by cell currents of the memory cells, respectively and by reference currents of the reference cells, respectively;

means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell and the reference currents;

writing means for applying a writing voltage to at least a selected one of the memory cells; and

control means for enabling the writing means during at least part of the application of the biasing voltage after determining the condition of each memory cell.

2. The refresh circuit according to claim 1, wherein the control means includes verifying means for detecting a warning condition of each memory cell when a difference between a corresponding threshold voltage and a reference threshold voltage is lower than a safe margin, the memory cells being selected for the application of the writing voltage in response to the detection of the warning condition.

3. The refresh circuit according to claim 2, wherein the reading means further includes means for applying the biasing voltage to a set of further reference cells each one of the further reference cells having a further reference threshold voltage, a difference between each further reference threshold voltage and a corresponding reference threshold voltage being equal to the safe margin, and wherein the verifying means includes means for detecting the reaching of the comparison current by a further reference current of each further reference cell, and means for determining the warning condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell, the reference current and the further reference current.

4. The refresh circuit according to claim 3, wherein the means for determining the warning condition includes:

means for providing a guard signal asserted when the biasing voltage is comprised between the reference threshold voltage and a corresponding further reference threshold voltage; and

means for latching the guard signal in response to the reaching of the comparison current by the cell current, the means for providing the guard signal including means for setting the guard signal alternatively to a bit changing between each pair of consecutive logical values stored in one of the memory cells or to said bit being inverted, and means for exchanging the bit and the inverted bit in response to the detection of the reaching of the comparison current by each further reference current.

5. The refresh circuit according to claim 2, wherein the verifying means includes:

means for delaying the detection of the reaching of the comparison current by each reference current according to a delay, a change of the biasing voltage corresponding to the delay being equal to the safe margin; and

means for determining the warning condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell, the reaching of the comparison current by the reference currents, and the delayed detection of the reaching of the comparison current by the reference currents.

6. The refresh circuit according to claim 5, wherein the means for determining the warning condition includes:

means for providing a guard signal asserted when the biasing voltage is comprised between the reference threshold voltage and a corresponding further reference threshold voltage, the means for delaying the detection including means for delaying the guard signal, and means for latching the guard signal in response to the reaching of the comparison current by the cell current, the means for providing the guard signal including means for setting the guard signal alternatively to a bit changing between each pair of consecutive logical values stored in one of the memory cells or to said bit being inverted, and means for exchanging the bit and the inverted bit in response to each assertion of the delayed guard signal.

7. The refresh circuit according to claim 2, wherein the control means includes means for enabling the writing means from the detection of the warning condition to a completion of the reading of the set of memory cells.

8. The refresh circuit according to claim 2, wherein the control means includes means for enabling the writing means for a time interval from the detection of the warning condition.

9. The refresh circuit according to claim 2, wherein the control means includes means for enabling the writing means from the detection of the reaching of the comparison current by the reference current of a last reference cell having a highest threshold voltage in absolute value to a completion of the reading of the set of memory cells.

10. A memory device comprising:

a plurality of memory cells;

means for addressing a set of memory cells;

a set of reference cells each one having a reference threshold voltage; and

a refresh circuit having;

reading means for reading the plurality of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the plurality of memory cells and to the set of reference cells,

means for detecting reaching of a comparison current by cell currents of the plurality of memory cells, respectively and by reference currents of the reference cells, respectively,

means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell and the reference currents,

writing means for applying a writing voltage to at least a selected one of the plurality of memory cells, and

control means for enabling the writing means during at least part of the application of the biasing voltage after determining the condition of each memory cell.

11. The memory device of claim 10 wherein the control means includes verifying means for detecting a warning condition of each memory cell when a difference between a corresponding threshold voltage and a reference threshold voltage is lower than a safe margin, the plurality of memory cells being selected for applying the writing voltage in response to the detection of the warning condition.

12. The memory device of claim 11 wherein the reading means further includes means for applying the biasing voltage to a set of further reference cells each one of the set of further reference cells having a further reference threshold voltage, a difference between each further reference threshold voltage and a corresponding reference threshold voltage being equal to the safe margin, and wherein the verifying means includes means for detecting the reaching of the comparison current by a further reference current of each further reference cell, and means for determining the warning condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell, the reference current and the further reference current.

13. The memory device of claim 12 wherein the means for determining the warming condition includes:

means for providing a guard signal asserted when the biasing voltage is comprised between the reference threshold voltage and a corresponding further reference threshold voltage; and

means for latching the guard signal in response to the reaching of the comparison current by the cell current, the means for providing the guard signal including means for setting the guard signal alternatively to a bit changing between each pair of consecutive logical values stored in one of the memory cells or to said bit being inverted, and means for exchanging the bit and the inverted bit in response to the detection of the reaching of the comparison current by each further reference current.

14. A method of refreshing a memory device, the method comprising:

reading a set of memory cells, the step of reading including applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells each one of the reference cells having a reference threshold voltage;

detecting reaching of a comparison current by cell currents of the memory cells, respectively and by reference currents of the reference cells, respectively;

determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell and the reference currents;

applying a writing voltage to at least a selected one of the memory cells; and

enabling the application of the writing voltage during at least part of the application of the biasing voltage after determining the condition of each memory cell.

15. The method of claim 14, further comprising:

detecting a warning condition of each memory cell when a difference between a corresponding threshold voltage and a reference threshold voltage is lower than a safe margin, the memory cells being selected for the application of the writing voltage in response to detecting the warning condition.

16. The method of claim 15 wherein reading the set of memory cells includes:

applying the biasing voltage to a set of further reference cells each one of the further reference cells having a further reference threshold voltage, a difference between each further reference threshold voltage and a corresponding reference threshold voltage being equal to the safe margin.

17. The method of claim 16 wherein detecting the warning condition includes detecting the reaching of the comparison current by a further reference current of each further reference cell, and determining the warning condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell, the reference current and the further reference current.

18. The method of claim 17 wherein determining the warning condition includes:

providing a guard signal asserted when the biasing voltage is comprised between the reference threshold voltage and a corresponding further reference threshold voltage; and

latching the guard signal in response to the reaching of the comparison current by the cell current, providing the guard signal includes setting the guard signal alternatively to a bit changing between each pair of consecutive logical values stored in one of the memory cells or to said bit being inverted, and exchanging the bit and the inverted bit in response to the detection of the reaching of the comparison current by each further reference current.

19. A memory device comprising:

a plurality of memory cells;

a decoder to address the plurality of memory cells;

a set of reference cells having reference threshold voltages, respectively; and

a refresh circuit including;

a reading circuit structured to read the plurality of memory cells, the reading circuit including a biasing circuit applying a biasing voltage with a substantially monotone time pattern to the plurality of memory cells and to the set of reference cells,

a sense amplifier structured to detect whether respective cell currents of the memory cells and respective reference currents of the reference cells exceed a comparison current,

an encoder structured to determine respective current logical values to be stored in the memory cells, respectively, according to respective temporal relations of the comparison current with the respective cell current and reference current,

a soft-program load structured to apply a writing voltage to one of the plurality of memory cells, and

a control circuit structured to enable the soft-program load during at least part of the application of the biasing voltage after the determination of the current logical values to be stored in the memory cells.

20. The memory device of claim 19 wherein the control circuit includes a detection circuit operable to detect a warning condition of each of the plurality of memory cells when a difference between a corresponding threshold voltage and a reference threshold voltage is lower than a safe margin, the plurality of memory cells being selected for having the writing voltage applied therein in response to the detection of the warning condition.

21. The memory device of claim 20 wherein the reading circuit further includes a further biasing circuit operable to apply the biasing voltage to a set of further reference cells each one of the further reference cells having a further reference threshold voltage, a difference between each further reference threshold voltage and a corresponding reference threshold voltage being equal to the safe margin, and wherein the detection circuit includes a further detection circuit operable to detect the reaching of the comparison current by a further reference current of each further reference cell, and a determination circuit operable to determine the warning condition of each of the plurality of memory cells according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell, the reference current and the further reference current.