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Method and system for refreshing a memory device during reading thereof

  • US 7,417,900 B2
  • Filed: 04/02/2007
  • Issued: 08/26/2008
  • Est. Priority Date: 04/03/2006
  • Status: Active Grant
First Claim
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1. A refresh circuit for refreshing a memory device, the refresh circuit comprising:

  • reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells, each one of the reference cells having a reference threshold voltage;

    means for detecting reaching of a comparison current by cell currents of the memory cells, respectively and by reference currents of the reference cells, respectively;

    means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell and the reference currents;

    writing means for applying a writing voltage to at least a selected one of the memory cells; and

    control means for enabling the writing means during at least part of the application of the biasing voltage after determining the condition of each memory cell.

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