Method and system for refreshing a memory device during reading thereof
First Claim
1. A refresh circuit for refreshing a memory device, the refresh circuit comprising:
- reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells, each one of the reference cells having a reference threshold voltage;
means for detecting reaching of a comparison current by cell currents of the memory cells, respectively and by reference currents of the reference cells, respectively;
means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell and the reference currents;
writing means for applying a writing voltage to at least a selected one of the memory cells; and
control means for enabling the writing means during at least part of the application of the biasing voltage after determining the condition of each memory cell.
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Abstract
A refresh circuit for refreshing a memory device is proposed. The refresh circuit includes: reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells each one having a reference threshold voltage, means for detecting the reaching of a comparison current by a cell current of each memory cell and by a reference current of each reference cell, and means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and the reference currents, and writing means for applying a writing voltage to at least one selected of the memory cells; the refresh circuit further includes control means for enabling the writing means during at least part of the application of the biasing voltage after the determination of the condition of each selected memory cell.
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Citations
21 Claims
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1. A refresh circuit for refreshing a memory device, the refresh circuit comprising:
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reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells, each one of the reference cells having a reference threshold voltage; means for detecting reaching of a comparison current by cell currents of the memory cells, respectively and by reference currents of the reference cells, respectively; means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell and the reference currents; writing means for applying a writing voltage to at least a selected one of the memory cells; and control means for enabling the writing means during at least part of the application of the biasing voltage after determining the condition of each memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory device comprising:
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a plurality of memory cells; means for addressing a set of memory cells; a set of reference cells each one having a reference threshold voltage; and a refresh circuit having; reading means for reading the plurality of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the plurality of memory cells and to the set of reference cells, means for detecting reaching of a comparison current by cell currents of the plurality of memory cells, respectively and by reference currents of the reference cells, respectively, means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell and the reference currents, writing means for applying a writing voltage to at least a selected one of the plurality of memory cells, and control means for enabling the writing means during at least part of the application of the biasing voltage after determining the condition of each memory cell. - View Dependent Claims (11, 12, 13)
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14. A method of refreshing a memory device, the method comprising:
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reading a set of memory cells, the step of reading including applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells each one of the reference cells having a reference threshold voltage; detecting reaching of a comparison current by cell currents of the memory cells, respectively and by reference currents of the reference cells, respectively; determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the cell current of the memory cell and the reference currents; applying a writing voltage to at least a selected one of the memory cells; and enabling the application of the writing voltage during at least part of the application of the biasing voltage after determining the condition of each memory cell. - View Dependent Claims (15, 16, 17, 18)
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19. A memory device comprising:
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a plurality of memory cells; a decoder to address the plurality of memory cells; a set of reference cells having reference threshold voltages, respectively; and a refresh circuit including; a reading circuit structured to read the plurality of memory cells, the reading circuit including a biasing circuit applying a biasing voltage with a substantially monotone time pattern to the plurality of memory cells and to the set of reference cells, a sense amplifier structured to detect whether respective cell currents of the memory cells and respective reference currents of the reference cells exceed a comparison current, an encoder structured to determine respective current logical values to be stored in the memory cells, respectively, according to respective temporal relations of the comparison current with the respective cell current and reference current, a soft-program load structured to apply a writing voltage to one of the plurality of memory cells, and a control circuit structured to enable the soft-program load during at least part of the application of the biasing voltage after the determination of the current logical values to be stored in the memory cells. - View Dependent Claims (20, 21)
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Specification