Semiconductor memory device employing clamp for preventing latch up
First Claim
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1. A semiconductor memory device comprising:
- means for precharging and equalizing a pair of bit lines; and
means for generating a control signal which controls enable and disable of the precharging/equalizing means,wherein the control signal generating means includesa CMOS transistor; and
a clamping means wherein the clamping means to clamp a source voltage transferred to the CMOS transistor uses a bulk bias voltage of the CMOS transistor in order to reduce a latch-up phenomenon caused by the CMOS transistor,wherein the control signal generating means includesa PMOS transistor; and
an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving an output voltage of the clamping means as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving a ground voltage as its source voltage.
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Abstract
A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing unit, wherein the control signal generating unit includes a clamping unit to clamp its source voltage to a voltage level lower than that of its bulk bias.
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Citations
19 Claims
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1. A semiconductor memory device comprising:
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means for precharging and equalizing a pair of bit lines; and means for generating a control signal which controls enable and disable of the precharging/equalizing means, wherein the control signal generating means includes a CMOS transistor; and a clamping means wherein the clamping means to clamp a source voltage transferred to the CMOS transistor uses a bulk bias voltage of the CMOS transistor in order to reduce a latch-up phenomenon caused by the CMOS transistor, wherein the control signal generating means includes a PMOS transistor; and an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving an output voltage of the clamping means as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving a ground voltage as its source voltage. - View Dependent Claims (2)
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3. A semiconductor memory device comprising:
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means for precharging and equalizing a pair of bit lines; and means for generating a control signal which controls enable and disable of the precharging/equalizing means, wherein the control signal generating means includes a CMOS transistor; and a clamping means wherein the clamping means to clamp a source voltage transferred to the CMOS transistor uses a bulk bias voltage of the CMOS transistor in order to reduce a latch-up phenomenon caused by the CMOS transistor, wherein the control signal generating means includes a PMOS transistor; and an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving a supply voltage as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving an output voltage of the clamping means as its source voltage. - View Dependent Claims (4)
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5. A semiconductor memory device comprising:
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a sense amplifier, connected to a pair of bit lines, for amplifying electric potential difference of the bit line pair; a sense amplifier driver which includes means for precharging and equalizing a driving voltage line of the sense amplifier and drives the sense amplifier driving voltage line; and a control signal generating means which produces a control signal to control enable and disable of the precharging/equalizing means in the sense amplifier driver, wherein the control signal generating means includes a CMOS transistor; and a clamping means wherein the clamping means to clamp a source voltage transferred to the CMOS transistor using a bulk bias voltage the CMOS transistor in order to reduce a latch-up phenomenon caused by the CMOS transistor, wherein the control signal generating means includes a PMOS transistor; and an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving an output voltage of the clamping means as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving a ground voltage as its source voltage. - View Dependent Claims (6)
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7. A semiconductor memory device comprising:
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a sense amplifier, connected to a pair of bit lines, for amplifying electric potential difference of the bit line pair; a sense amplifier driver which includes means for precharging and equalizing a driving voltage line of the sense amplifier and drives the sense amplifier driving voltage line; and a control signal generating means which produces a control signal to control enable and disable of the precharging/equalizing means in the sense amplifier driver, wherein the control signal generating means includes a CMOS transistor; and a clamping means wherein the clamping means to clamp a source voltage transferred to the CMOS transistor using a bulk bias voltage the CMOS transistor in order to reduce a latch-up phenomenon caused by the CMOS transistor, wherein the control signal generating means includes a PMOS transistor; and an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving a supply voltage as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving an output voltage of the clamping means as its source voltage. - View Dependent Claims (8)
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9. A semiconductor memory device comprising:
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a pair of data lines; means including a first CMOS transistor for driving an input signal to the data line pair; means including a second CMOS transistor for precharging and equalizing the data line pair; a first clamping means for clamping a source voltage transferred to the first CMOS transistor of the data line driving means using a bulk bias of the first CMOS transistor in order to reduce a latch-up phenomenon caused by the frist CMOS transistor; and a second clamping means for clamping a source voltage transferred to the second CMOS transistor of the precharging/equalizing means using the second CMOS transistor in order to reduce a latch-up phenomenon caused by the second CMOS transistor, wherein the driving means includes a PMOS transistor; and an NMOS transistor which are connected to the data line pair and whose gates receives a control signal and drains commonly form an output node connected to the data line, the PMOS transistor using a boosted voltage as a bulk bias and receiving an output voltage of the first clamping means as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving a ground voltage as its source voltage. - View Dependent Claims (10, 11, 12)
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13. A semiconductor memory device comprising:
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a pair of data lines; means including a first CMOS transistor for driving an input signal to the data line pair; means including a second CMOS transistor for precharging and equalizing the data line pair; a first clamping means for clamping a source voltage transferred to the first CMOS transistor of the data line driving means using a bulk bias of the first CMOS transistor in order to reduce a latch-up phenomenon caused by the frist CMOS transistor; and a second clamping means for clamping a source voltage transferred to the second CMOS transistor of the precharging/equalizing means using the second CMOS transistor in order to reduce a latch-up phenomenon caused by the second CMOS transistor, wherein the driving means includes a PMOS transistor; and an NMOS transistor which are connected to the data line pair and whose gates receives a control signal and drains commonly form an output node connected to the data line, the PMOS transistor using a boosted voltage as a bulk bias and receiving a supply voltage as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving an output voltage of the first clamping means as its source voltage. - View Dependent Claims (14)
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15. A semiconductor memory device comprising:
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a pair of local data input/output (I/O) lines and a pair of segment data input/output (I/O) lines; an isolation switching means for controlling transmission between the segment data I/O line pair and the local data I/O line pair; means for equalizing the segment data I/O line pair and the local data I/O line pair; and means for generating a control signal used to control enable and disable of the equalizing means, wherein the control signal generating means includes a CMOS transistor and a clamping means wherein the clamping means to clamp a source voltage transferred to the CMOS transistor uses a bulk bias voltage of the CMOS transistor in order to reduce a latch-up phenomenon caused by the CMOS transistor. - View Dependent Claims (16, 17, 18, 19)
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Specification