Semiconductor memory device

• US 7,417,914 B2
• Filed: 06/15/2007
• Issued: 08/26/2008
• Est. Priority Date: 11/09/2001
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Shimizu, Hiroshi, Yokozeki, Wataru
• Primary Examiner(s): Yoha; Connie C
• Application Number:
  US11/812,144
• Publication Number:
  US 20070247956A1
• Time in Patent Office: 438 Days
• Field of Search: 365/230.03, 365/154, 365/156, 365/189.01, 365/230.08
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.

Claims

1. A semiconductor memory device in which memory cells arranged in a column direction are divided into a plurality of local blocks, in which data is read or written by the local block, and in which each local block has a read error protection circuit for preventing a read error from occurring in the case of data being read from a memory cell, the read error protection circuit including:

a first transistor having an input terminal connected to an auxiliary connection line of a memory cell included in the local block, a first output terminal connected to a main common bit line for reading data from or writing data into a local block included in each column is connected, and a second output terminal connected to a constant high-level voltage power supply; and

a second transistor having an input terminal connected to a main connection line of a memory cell included in the local block, a first output terminal connected to an auxiliary common bit line for reading data from or writing data into a local block included in each column, and a second output terminal connected to the constant high-level voltage power supply.