Image decoding apparatus

• US 7,418,146 B2
• Filed: 02/10/2005
• Issued: 08/26/2008
• Est. Priority Date: 02/10/2004
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Okada, Shigeyuki, Watanabe, Tsuyoshi
• Primary Examiner(s): Bella; Matthew C.
• Assistant Examiner(s): Bayat; Ali
• Application Number:
  US11/054,537
• Publication Number:
  US 20050175250A1
• Time in Patent Office: 1,293 Days
• Field of Search: 382232-233, 382/238, 382/244, 382/247, 382/246, 382/240, 382250-252, 35842601-42616, 37524001-24016, 341/107, 341/50
• US Class Current: 382/247
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/63 using sub-band based transform, e.g. wavelets

Abstract

Coded data are inputted from a stream analyzing unit to an entropy decoding unit. A group of peripheral information registers stores peripheral information on a target pixel for estimating a context used for arithmetic decoding of the coded data. Based on the peripheral information stored in the group of peripheral registers, a context estimation unit estimates a context and delivers the estimated context to an arithmetic decoding unit. The arithmetic decoding unit decodes the coded data based on a context label, then derives a decision and supplies the decision to an inverse quantization unit. The peripheral information stored in the group of peripheral registers is updated by a decoding result of the arithmetic decoding unit in the same cycle as the decoding.

Claims

1. An image decoding apparatus, including:

a peripheral information register which stores peripheral information on a pixel when the pixel is decoded;

a context estimation unit which generates context information for estimating a decoding result of the pixel by reading out the peripheral information from said peripheral information register; and

a decoding unit which decodes the pixel from the context information generated by said context estimation unit and coded data of the pixel,

wherein said decoding unit decodes one pixel for each unit decoding period and at the time of termination of the each unit decoding period said decoding unit updates the peripheral information by the decoding result of the pixel that has been decoded during the unit decoding period and then writes back the updated peripheral information to said peripheral information register.

2. An image decoding apparatus according to claim 1, wherein said peripheral information register stores peripheral information on an entire pixel block to be processed, has output bus width which is less than a bit number of the peripheral information to be stored and stores the peripheral information by a ring buffer scheme so that necessary peripheral information is read out sequentially.

3. An image decoding apparatus according to claim 1, wherein in a certain unit decoding period said context estimation unit generates, in advance, context information needed in a next unit decoding period and stores the thus generated context information.

4. An image decoding apparatus, comprising:

an entropy decoding block which entropy-decodes a coded image;

an inverse quantization unit which inverse-quantizes entropy-decoded data; and

an inverse transform unit which performs a spatial-frequency inverse-transform on the inverse-quantized data,

said entropy decoding block including;

a peripheral information register which stores peripheral information on a pixel when the pixel is decoded;

a context estimation unit which generates context information for estimating a decoding result of the pixel by reading out the peripheral information from the peripheral information register; and

a decoding unit which decodes the pixel from the context information generated by the context estimation unit and coded data of the pixel,

wherein the decoding unit decodes one pixel for each unit decoding period and at the time of termination of the each unit decoding period said decoding unit updates the peripheral information by the decoding result of the pixel that has been decoded during the unit decoding period and then writes back the updated peripheral information to the peripheral information register.

5. An image decoding apparatus according to claim 4, wherein the peripheral information register stores peripheral information on an entire pixel block to be processed, has output bus width which is less than a bit number of the peripheral information to be stored and stores the peripheral information by a ring buffer scheme so that necessary peripheral information is read out sequentially.

6. An image decoding apparatus according to claim 4, wherein in a certain unit decoding period the context estimation unit generates, in advance, context information needed in a next unit decoding period and stores the thus generated context information.