Memory hub and method for providing memory sequencing hints

• US 7,418,526 B2
• Filed: 04/19/2006
• Issued: 08/26/2008
• Est. Priority Date: 03/29/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US11/408,285
• Publication Number:
  US 20060212666A1
• Time in Patent Office: 860 Days
• Field of Search: 711154-160, 711/137, 711/169, 711144-146, 710 5- 7, 710/29, 710 15- 19, 710 36- 39, 710/74, 712233-240
• US Class Current: 710/5
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of the subsequent operation of the memory devices. The memory module uses the hint to adjust the operation of the memory module, such as the number of pages to remain open or cache lines to be fetched.

Claims

1. A memory module, comprising:

a plurality of memory devices; and

a memory hub coupled to the memory devices, the memory hub comprising;

a link interface receiving memory requests for access to memory cells in at least one of the memory devices, at least some of the memory requests including respective memory hints providing information about the subsequent operation of the memory devices;

a memory device interface coupled to the memory devices and to the link interface, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and

a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability of the memory devices responsive to the memory hints.

2. The memory module of claim 1 wherein the memory devices are disposed on a substrate.

3. The memory module of claim 2 wherein the memory hub is disposed on the substrate.

4. The memory module of claim 1 wherein the link interface comprises an optical input/output port.

5. The memory module of claim 1 wherein at least one of the hints comprises signals placing the memory devices in a page mode.

6. The memory module of claim 5 wherein at least one of the hints comprises a number of pages to remain open.

7. The memory module of claim 1 wherein at least one of the hints comprises a prefetching hint.

8. The memory module of claim 1 wherein at least one of the hints comprises a number of cache lines that will be sent.

9. The memory module of claim 1 wherein at least one of the hints comprises a stride indicative of a sequence of addresses from which data are to be fetched.

10. The memory module of claim 1 wherein at least one of the hints comprises a number of cache lines to skip.

11. The memory module of claim 1 wherein the memory devices comprise dynamic random access memory devices.

12. The memory module of claim 1, further comprising a request decoder coupled to the link interface and the memory sequencer, the request decoder being operable to decode the hint in the memory requests.

13. A memory hub, comprising:

a link interface receiving memory requests for access to memory cells in at least one of the memory devices, at least some of the memory requests including respective memory hints providing information about the subsequent operation of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and

a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability of the memory devices responsive to the memory hints.

14. The memory hub of claim 13 wherein the link interface comprises an optical input/output port.

15. The memory hub of claim 13 wherein at least one of the hints comprises signals placing the memory devices in a page mode.

16. The memory hub of claim 15 wherein at least one of the hints comprises a number of pages to remain open.

17. The memory hub of claim 13 wherein at least one of the hints comprises a prefetching hint.

18. The memory hub of claim 13 wherein at least one of the hints comprises a number of cache lines that will be sent.

19. The memory hub of claim 13 wherein at least one of the hints comprises a stride indicative of a sequence of addresses from which data are to be fetched.

20. The memory hub of claim 13 wherein at least one of the hints comprises a number of cache lines to skip.

21. The memory hub of claim 13 wherein the memory devices comprise dynamic random access memory devices.

22. The memory hub of claim 13 further comprising a request decoder coupled to the link interface and the memory sequencer, the request decoder being operable to decode the hint.

23. A method of adjusting memory sequencing in a memory module containing a plurality of memory devices, comprising:

generating memory requests for access to a memory device mounted on the memory module, at least some of the memory request including a memory hint, the memory hint being other than a page hint indication;

providing information about the subsequent operation of the memory devices;

receiving the memory requests at the memory module;

adjusting operability of the memory module based on the memory hint; and

coupling the memory request to the memory device responsive to the received memory request.

24. The method of claim 23 wherein the act of adjusting operability of the memory module based on the memory hint comprises adjusting operability of the memory sequencer based on the memory hint.

25. The method of claim 23 wherein the act of adjusting operability of the memory module based on the memory hint comprises adjusting operability of the memory devices based on the memory hint.

26. The method of claim 23 wherein the act of coupling the memory request to the memory device comprises coupling the memory request over a link interface comprising an optical input/output port.

27. The method of claim 23 wherein the act of adjusting operability of the memory module comprises placing the memory devices in page mode.

28. The method of claim 23 wherein act of adjusting operability of the memory module comprises leaving a number of pages open.

29. The method of claim 23 wherein the hint generated by the system controller comprises a prefetching hint.

30. The method of claim 23 wherein the hint generated by the system controller comprises a number of cache lines that will be sent.

31. The method of claim 23, wherein the hint generated by the system controller comprises a stride indicative of a sequence of addresses from which data are to be fetched.

32. The method of claim 23 wherein the hint comprises a number of cache lines to skip.

33. The method of claim 23 wherein the memory devices comprise dynamic random access memory devices.

34. The method of claim 23 further comprising decoding the hint with a request decoder.