Memory interleaving

• US 7,418,571 B2
• Filed: 04/22/2005
• Issued: 08/26/2008
• Est. Priority Date: 01/10/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rosenbluth, Mark B., Wolrich, Gilbert, Adiletta, Matthew J.
• Primary Examiner(s): Bragdon; Reginald
• Assistant Examiner(s): DINH, NGOC V
• Application Number:
  US11/112,047
• Publication Number:
  US 20050185437A1
• Time in Patent Office: 1,222 Days
• Field of Search: None
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0607 Interleaved addressing

Abstract

Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.

Claims

1. A method comprising:

receiving an address corresponding to a memory having a non power of two number, X, of associated channels to the memory;

determining one or more of the channels to use in accessing the memory, the determining comprising applying a modulo-X based reduction to the address; and

indexing the address for a determined channel;

wherein the receiving comprises receiving a first address and a count, the method further comprising calculating a second address from the first address and the count, and the determining comprises applying the modulo-X based reduction to the first and second addresses to map the first and second addresses to the channels, wherein a single one of the channels is determined to be used in accessing the memory in response to receiving the first address if both the first and second addresses map to the single one of the channels.

2. The method of claim 1, wherein the applying the modulo-X based reduction to the address comprises including a channel number as input to the modulo-X based reduction.

3. A method comprising:

receiving an address corresponding to a memory having a non power of two number, X, of associated channels to the memory;

determining one or more of the channels to use in accessing the memory, the determining comprising applying a modulo-X based reduction to the address; and

indexing the address for a determined channel;

wherein the indexing comprises;

determining a longest string of consecutive bits having a value of one in the address;

dropping the longest string from the address;

justifying remaining bits in the address; and

filling vacated bits in the address with ones to create a remapped address for the determined channel.

4. The method of claim 3, wherein the determined channel has a non power of two number of corresponding memory locations, and the filling comprises filling the vacated bits in the address based on one or more lookup tables including constants that indicate start addresses for address filling.

5. An apparatus comprising:

a non power of two number, X, of channels to a memory; and

a control device configured to receive an address corresponding to the memory and determine one or more of the channels to use in accessing the memory by applying a modulo-X based reduction to the address;

wherein the address comprises a first address, the control device configured to receive the first address and a count, calculate a second address from the first address and the count, and determine the one or more of the channels by applying the modulo-X based reduction to the first and second addresses to map the first and second addresses to the channels, wherein a single one of the channels is determined to be used in accessing the memory in response to receipt of the first address if both the first and second addresses map to the single one of the channels.

6. The apparatus of claim 5, wherein the applying the modulo-X based reduction to the address comprises including a channel number as input to the modulo-X based reduction.

13. A system comprising:

the apparatus of claim 5, 7 or 9; and

the memory comprising a read-write memory.

14. The system of claim 13, wherein the read-write memory comprises a random access memory.

15. The system of claim 13, further comprising multiple additional devices configured to access the read-write memory using the control device.

16. The system of claim 15, wherein the multiple additional devices comprise multiple processors.

7. An apparatus comprising:

a non power of two number, X, of channels to a memory; and

a control device configured to receive an address corresponding to the memory and determine one or more of the channels to use in accessing the memory by applying a modulo-X based reduction to the address, the control device configured to determine a longest string of consecutive bits having a value of one in the address, drop the longest string from the address, justify remaining bits in the address, and fill vacated bits in the address with ones to create a remapped address for the determined channel.

8. The apparatus of claim 7, wherein the determined channel has a non power of two number of corresponding memory locations, and the control device configured to fill the vacated bits in the address based on one or more lookup tables including constants that indicate start addresses for address filling.

9. An apparatus comprising:

a non power of two number, X, of channels to a memory; and

a control device configured to receive an address corresponding to the memory and determine one or more of the channels to use in accessing the memory by applying a modulo-X based reduction to the address;

wherein the control device comprises X channel controllers, each of the channel controllers configured to receive the address corresponding to the memory and determine whether an associated channel is to be used in accessing the memory by applying the modulo-X based reduction to the address; and

wherein the address comprises a first address, each of the channel controllers comprises a match detect mechanism and a count remapping mechanism, the match detect mechanism configured to receive the first address and a count, calculate a second address from the first address and the count, and determine whether the associated channel is to be used in accessing the memory by applying the modulo-X based reduction to the first and second addresses, and the count remapping mechanism configured to receive the first address and the count and to remap the count.

10. The apparatus of claim 9, the count remapping mechanism further configured to index a third address within the associated channel.

11. The apparatus of claim 10, the count remapping mechanism configured to determine a longest string of consecutive bits having a value of one in the third address, drop the longest string from the third address, justify remaining bits in the third address, and fill vacated bits in the third address with ones to create a remapped address within the associated channel.

12. The apparatus of claim 11, wherein the associated channel has a non power of two number of corresponding memory locations, and the count remapping mechanism configured to fill the vacated bits in the third address based on one or more lookup tables including constants that indicate start addresses for address filling.