System for representing the logical and physical information of an integrated circuit
First Claim
1. A processor-based method for floor planning an integrated circuit design, comprising:
- establishing in a memory arrangement a plurality of physical blocks in response to user input, wherein each physical block has associated data that indicates a physical area of an integrated circuit to be occupied by logic assigned to the physical block;
assigning each logic block of a logic block hierarchy to one of the plurality of physical blocks in response to user input;
in response to assigning a first logic block to one of the physical blocks, traversing the logic block hierarchy beginning at the first logic block and assigning all children logic blocks of the first logic block to the physical block;
creating pins and nets that connect logic blocks assigned to the physical blocks as a function of locations of the physical blocks on the integrated circuit and connections defined by the logic block hierarchyreassigning, in response to user input, a child logic block of a first logic block that is assigned to a first physical block to a second physical block;
de-assigning the first logic block from the first physical block in response to the first logic block having children logic blocks assigned to different physical blocks;
wherein each physical block has associated data that indicates each logic block assigned to the physical block;
determining from the logic block hierarchy children blocks of the first logic block; and
determining from the physical blocks whether any children logic blocks of the first logic block are assigned to different physical blocks.
1 Assignment
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Accused Products
Abstract
A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains a list of pins for the instances within the pblock. Net data structures in the physical hierarchy define which nets are connected to which pins.
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Citations
15 Claims
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1. A processor-based method for floor planning an integrated circuit design, comprising:
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establishing in a memory arrangement a plurality of physical blocks in response to user input, wherein each physical block has associated data that indicates a physical area of an integrated circuit to be occupied by logic assigned to the physical block; assigning each logic block of a logic block hierarchy to one of the plurality of physical blocks in response to user input; in response to assigning a first logic block to one of the physical blocks, traversing the logic block hierarchy beginning at the first logic block and assigning all children logic blocks of the first logic block to the physical block; creating pins and nets that connect logic blocks assigned to the physical blocks as a function of locations of the physical blocks on the integrated circuit and connections defined by the logic block hierarchy reassigning, in response to user input, a child logic block of a first logic block that is assigned to a first physical block to a second physical block; de-assigning the first logic block from the first physical block in response to the first logic block having children logic blocks assigned to different physical blocks; wherein each physical block has associated data that indicates each logic block assigned to the physical block; determining from the logic block hierarchy children blocks of the first logic block; and determining from the physical blocks whether any children logic blocks of the first logic block are assigned to different physical blocks. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A system for floor planning an integrated circuit design, comprising:
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a computer display; a user-input device; a computing arrangement coupled to the computer display and to the user input device, the computing arrangement configured to, establish a plurality of physical blocks in response to user input, wherein each physical block has associated data that indicates a physical area of an integrated circuit to be occupied by logic assigned to the physical block; assign each logic block of a logic block hierarchy to one of the plurality of physical blocks in response to user input; output to the display representations of the plurality of physical blocks and assigned logic blocks; in response to assigning a first logic block to one of the physical blocks, traverse the logic block hierarchy beginning at the first logic block and assign all children logic blocks of the first logic block to the physical block; create pins and nets that connect logic blocks assigned to the physical blocks as a function of locations of the physical blocks on the integrated circuit and connections defined by the logic block hierarchy reassign a child logic block of a first logic block that is assigned to a first physical block, to a second physical block in response to user input; de-assign the first logic block from the first physical block in response to the first logic block having children logic blocks assigned to different physical blocks; wherein each physical block has associated data that indicates each logic block assigned to the physical block; determine from the logic block hierarchy children blocks of the first logic block; and determine from the Physical blocks whether any children logic blocks of the first logic block are assigned to different physical blocks. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A processor-based method for floor planning an integrated circuit design, comprising:
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establishing in a memory arrangement a plurality of physical blocks in response to user input, wherein each physical block has associated data that indicates a physical area of an integrated circuit to be occupied by logic assigned to the physical block; assigning each logic block of a logic block hierarchy to one of the plurality of physical blocks in response to user input; in response to assigning a first logic block to one of the physical blocks, traversing the logic block hierarchy beginning at the first logic block and assigning all children logic blocks of the first logic block to the physical block; creating pins and nets that connect logic blocks assigned to the physical blocks as a function of locations of the physical blocks on the integrated circuit and connections defined by the logic block hierarchy; wherein assigning includes establishing a corresponding pointer from a physical block to a logic block in the logic block hierarchy for each logic block assigned to the physical block; reassigning, in response to user input, a child logic block of a first logic block that is assigned to a first physical block, to a second physical block, removing a pointer from the first physical block to the child block in the logic block hierarchy, and adding a pointer from the second physical block to the child block in the logic block hierarchy; and removing a pointer from the first physical block to the first logic block in the logic block hierarchy in response to the first logic block having children logic blocks assigned to different physical blocks. - View Dependent Claims (14, 15)
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Specification