System for representing the logical and physical information of an integrated circuit

• US 7,418,686 B1
• Filed: 06/14/2005
• Issued: 08/26/2008
• Est. Priority Date: 03/03/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Knol, David A., Raje, Salil Ravindra
• Primary Examiner(s): Levin; Naum B
• Application Number:
  US11/152,502
• Time in Patent Office: 1,169 Days
• Field of Search: 716 8- 11
• US Class Current: 716/118
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains a list of pins for the instances within the pblock. Net data structures in the physical hierarchy define which nets are connected to which pins.

Claims

1. A processor-based method for floor planning an integrated circuit design, comprising:

establishing in a memory arrangement a plurality of physical blocks in response to user input, wherein each physical block has associated data that indicates a physical area of an integrated circuit to be occupied by logic assigned to the physical block;

assigning each logic block of a logic block hierarchy to one of the plurality of physical blocks in response to user input;

in response to assigning a first logic block to one of the physical blocks, traversing the logic block hierarchy beginning at the first logic block and assigning all children logic blocks of the first logic block to the physical block;

creating pins and nets that connect logic blocks assigned to the physical blocks as a function of locations of the physical blocks on the integrated circuit and connections defined by the logic block hierarchy

reassigning, in response to user input, a child logic block of a first logic block that is assigned to a first physical block to a second physical block;

de-assigning the first logic block from the first physical block in response to the first logic block having children logic blocks assigned to different physical blocks;

wherein each physical block has associated data that indicates each logic block assigned to the physical block;

determining from the logic block hierarchy children blocks of the first logic block; and

determining from the physical blocks whether any children logic blocks of the first logic block are assigned to different physical blocks.

2. The method of claim 1, further comprising, in response to reassigning a child logic block of a second logic block from a third physical block to a fourth physical block and in response to all children logic blocks of the second logic block being assigned to the fourth physical block, assigning the second logic block to the fourth physical block.

3. The method of claim 1, wherein assigning includes establishing a corresponding pointer from a physical block to a logic block in the logic block hierarchy for each logic block assigned to the physical block.

4. The method of claim 3, further comprising:

reassigning, in response to user input, a child logic block of a first logic block that is assigned to a first physical block, to a second physical block, removing a pointer from the first physical block to the child block in the logic block hierarchy, and adding a pointer from the second physical block to the child block in the logic block hierarchy; and

removing a pointer from the first physical block to the first logic block in the logic block hierarchy in response to the first logic block having children logic blocks assigned to different physical blocks.

5. The method of claim 4, further comprising:

determining from the logic block hierarchy children blocks of the first logic block; and

determining from pointers from the physical blocks to the logic block hierarchy whether any children logic blocks of the first logic block are assigned to different physical blocks.

6. The method of claim 5, further comprising, in response to reassigning a child logic block of a second logic block from a third physical block to a fourth physical block and in response to all children logic blocks of the second logic block being assigned to the fourth physical block, adding a pointer from the fourth physical block to the second logic block in the logic block hierarchy.

7. A system for floor planning an integrated circuit design, comprising:

a computer display;

a user-input device;

a computing arrangement coupled to the computer display and to the user input device, the computing arrangement configured to,

establish a plurality of physical blocks in response to user input, wherein each physical block has associated data that indicates a physical area of an integrated circuit to be occupied by logic assigned to the physical block;

assign each logic block of a logic block hierarchy to one of the plurality of physical blocks in response to user input;

output to the display representations of the plurality of physical blocks and assigned logic blocks;

in response to assigning a first logic block to one of the physical blocks, traverse the logic block hierarchy beginning at the first logic block and assign all children logic blocks of the first logic block to the physical block;

create pins and nets that connect logic blocks assigned to the physical blocks as a function of locations of the physical blocks on the integrated circuit and connections defined by the logic block hierarchy

reassign a child logic block of a first logic block that is assigned to a first physical block, to a second physical block in response to user input;

de-assign the first logic block from the first physical block in response to the first logic block having children logic blocks assigned to different physical blocks;

wherein each physical block has associated data that indicates each logic block assigned to the physical block;

determine from the logic block hierarchy children blocks of the first logic block; and

determine from the Physical blocks whether any children logic blocks of the first logic block are assigned to different physical blocks.

8. The system of claim 7, wherein the computing arrangement is further configured to, in response to reassignment of a child logic block of a second logic block from a third physical block to a fourth physical block and in response to all children logic blocks of the second logic block being assigned to the fourth physical block, assign the second logic block to the fourth physical block.

9. The system of claim 7, wherein the computing arrangement is further configured to establish a corresponding pointer from a physical block to a logic block in the logic block hierarchy for each logic block assigned to the physical block.

10. The system of claim 9, wherein the computing arrangement is further configured to:

reassign, in response to user input, a child logic block of a first logic block that is assigned to a first physical block, to a second physical block, remove a pointer from the first physical block to the child block in the logic block hierarchy, and add a pointer from the second physical block to the child block in the logic block hierarchy;

remove a pointer from the first physical block to the first logic block in the logic block hierarchy in response to the first logic block having children logic blocks assigned to different physical blocks.

11. The system of claim 10, wherein the computing arrangement is further configured to:

determine from the logic block hierarchy children blocks of the first logic block; and

determine from pointers from the physical blocks to the logic block hierarchy whether any children logic blocks of the first logic block are assigned to different physical blocks.

12. The system of claim 11, wherein the computing arrangement is further configured to, in response to reassigning a child logic block of a second logic block from a third physical block to a fourth physical block and in response to all children logic blocks of the second logic block being assigned to the fourth physical block, adding a pointer from the fourth physical block to the second logic block in the logic block hierarchy.

13. A processor-based method for floor planning an integrated circuit design, comprising:

establishing in a memory arrangement a plurality of physical blocks in response to user input, wherein each physical block has associated data that indicates a physical area of an integrated circuit to be occupied by logic assigned to the physical block;

assigning each logic block of a logic block hierarchy to one of the plurality of physical blocks in response to user input;

in response to assigning a first logic block to one of the physical blocks, traversing the logic block hierarchy beginning at the first logic block and assigning all children logic blocks of the first logic block to the physical block;

creating pins and nets that connect logic blocks assigned to the physical blocks as a function of locations of the physical blocks on the integrated circuit and connections defined by the logic block hierarchy;

wherein assigning includes establishing a corresponding pointer from a physical block to a logic block in the logic block hierarchy for each logic block assigned to the physical block;

reassigning, in response to user input, a child logic block of a first logic block that is assigned to a first physical block, to a second physical block, removing a pointer from the first physical block to the child block in the logic block hierarchy, and adding a pointer from the second physical block to the child block in the logic block hierarchy; and

removing a pointer from the first physical block to the first logic block in the logic block hierarchy in response to the first logic block having children logic blocks assigned to different physical blocks.

14. The method of claim 13, further comprising:

determining from the logic block hierarchy children blocks of the first logic block; and

determining from pointers from the physical blocks to the logic block hierarchy whether any children logic blocks of the first logic block are assigned to different physical blocks.

15. The method of claim 14, further comprising, in response to reassigning a child logic block of a second logic block from a third physical block to a fourth physical block and in response to all children logic blocks of the second logic block being assigned to the fourth physical block, adding a pointer from the fourth physical block to the second logic block in the logic block hierarchy.