Planarized and silicided trench contact
First Claim
1. A fabrication process for a power MOSFET comprising:
- forming a first trench in a substrate;
forming a second trench in the substrate;
doping a mesa in the substrate adjacent the first trench to form a vertical device including a source region, a channel region, and a drain region that are vertically aligned along a wall of the first trench;
forming a conductive gate structure that extends continuously from the first trench into the second trench, wherein the gate structure comprises a first portion that is in the first trench and acts as a gate of the vertical device, and a second portion that is in the second trench and forms a gate bus including a metal/silicide region;
planarizing a structure including the substrate and the conductive gate structure in the first and second trenches;
depositing a contact layer after planarizing the structure, wherein the contact layer includes a first region contacting the vertical device adjacent to the first trench and a second region overlying the second trench and contacting the gate bus; and
forming a first polysilicon layer that lines at least one of the first and second trenches;
depositing a metal on the first polysilicon layer;
etching the metal back to leave portions of the metal in depressions in the first polysilicon layer; and
depositing a second polysilicon layer so that the metal that is remaining on the first polysilicon layer is surrounded by polysilicon in at least one of the first and second trenches;
further comprising reacting the metal with the surrounding polysilicon to form suicide.
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Accused Products
Abstract
Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.
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Citations
17 Claims
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1. A fabrication process for a power MOSFET comprising:
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forming a first trench in a substrate; forming a second trench in the substrate; doping a mesa in the substrate adjacent the first trench to form a vertical device including a source region, a channel region, and a drain region that are vertically aligned along a wall of the first trench; forming a conductive gate structure that extends continuously from the first trench into the second trench, wherein the gate structure comprises a first portion that is in the first trench and acts as a gate of the vertical device, and a second portion that is in the second trench and forms a gate bus including a metal/silicide region; planarizing a structure including the substrate and the conductive gate structure in the first and second trenches; depositing a contact layer after planarizing the structure, wherein the contact layer includes a first region contacting the vertical device adjacent to the first trench and a second region overlying the second trench and contacting the gate bus; and forming a first polysilicon layer that lines at least one of the first and second trenches; depositing a metal on the first polysilicon layer; etching the metal back to leave portions of the metal in depressions in the first polysilicon layer; and depositing a second polysilicon layer so that the metal that is remaining on the first polysilicon layer is surrounded by polysilicon in at least one of the first and second trenches; further comprising reacting the metal with the surrounding polysilicon to form suicide. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A fabrication process for a power MOSFET comprising:
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forming a hard mask on a substrate; forming a first trench and a second trench in the substrate through openings in the hard mask; doping a mesa in the substrate adjacent the first trench to form a vertical device including a source region, a channel region, and a drain region that are vertically aligned along a wall of the first trench; forming a conductive gate structure that extends continuously from the first trench into the second trench, wherein the gate structure comprises a first portion that is in the first trench and acts as a gate of the vertical device, and a second portion that is in the second trench and forms a gate bus including a metal/silicide region; forming an insulating layer overlying the conductive gate structure; planarizing a structure including the insulating layer, wherein the planarizing exposes a region of the hard mask overlying the mesa and leaves the regions of the insulating layer in the openings in the hard mask; removing the hard mask without removing the regions of the insulating layer left after the planarizing; depositing a contact layer that includes a first region contacting the vertical device and the mesa where the region of the hard mask was removed and a second region overlying the second trench and contacting the gate bus, wherein the regions of the insulating layer separate the gate structure in the first trench from the contact layer; and forming a first polysilicon layer that lines at least one of the first and second trenches; depositing a metal on the first polysilicon layer; etching the metal back to leave portions of the metal in depressions in the first polysilicon layer; and depositing a second polysilicon layer so that the metal that is remaining on the first polysilicon layer is surrounded by polysilicon in at least one of the first and second trenches; further comprising reacting the metal with the surrounding polysilicon to form silicide. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification