Thin film transistor array substrate having main gate insulating film formed of organic material and sub gate insulating film formed of ferroelectric material and fabricating method thereof

• US 7,420,213 B2
• Filed: 04/25/2006
• Issued: 09/02/2008
• Est. Priority Date: 12/15/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Chae, Gee Sung, Heo, Jae Seok
• Primary Examiner(s): Jackson; Jerome
• Assistant Examiner(s): Ho; Anthony
• Application Number:
  US11/410,212
• Publication Number:
  US 20070138476A1
• Time in Patent Office: 861 Days
• Field of Search: 257/59, 257/72
• US Class Current: 257/72
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

A thin film transistor array substrate is provided. The thin film transistor array substrate includes a substrate; a gate pattern of a gate electrode and a gate line connected to the gate electrode on the substrate; a main gate insulating film formed of an organic material to cover the gate pattern; a semiconductor pattern overlapping the gate line such that the main gate insulating film is disposed between semiconductor patter and the gate line; a source/drain pattern on the semiconductor pattern. The source/drain pattern has a data line crossing the gate line with the main gate insulating film therebetween, a source electrode and a drain electrode, Here, the source electrode, the drain electrode and the semiconductor pattern define a thin film transistor disposed at the intersection between the gate line and the data line. The thin film transistor array substrate further includes a protective film defining a contact hole at a portion of the drain electrode; a pixel electrode contacting the drain electrode through the contact hole; and a sub gate insulating pattern disposed between the gate pattern and the main gate insulating film overlapping the gate pattern. The sub gate insulating pattern includes a ferroelectric material.

Claims

1. A thin film transistor array substrate, comprising:

a substrate;

a gate pattern on the substrate, the gate pattern including a gate electrode and a gate line connected to the gate electrode;

a main gate insulating film formed of an organic material to cover the gate pattern;

a semiconductor pattern overlapping the gate electrode such that the main gate insulating film is disposed between semiconductor pattern and the gate line;

a source/drain pattern on the semiconductor pattern, the source/drain pattern including a data line crossing the gate line with the main gate insulating film therebetween, a source electrode and a drain electrode, wherein thesource electrode, the drain electrode and the semiconductor pattern define a thin film transistor disposed at the intersection between the gate line and the data line;

a protective film having a contact hole at a portion of the drain electrode;

a pixel electrode contacting the drain electrode through the contact hole; and

a sub gate insulating pattern disposed between the gate pattern and the main gate insulating film overlapping the gate pattern, the sub gate insulating pattern including a ferroelectric material,

wherein the sub gate insulating pattern is only on the gate pattern and contacts the gate pattern, and

wherein a dielectric constant of the sub gate insulating pattern is greater than a dielectric constant of the main gate insulating film,

wherein the sub gate insulating pattern includes any one of lead zirconate titanate, lead lanthanum titanate, barium magnesium fluoride, bismuth titanate, strontium bismuth titanate, and strontium bismuth titanate niobate.

2. The thin film transistor array substrate as claimed in claim 1, wherein the sub gate insulating pattern, the main gate insulating film and the protective film, and the pixel electrode are disposed over the gate line to define a storage capacitor.

3. The thin film transistor array substrate as claimed in claim 1, wherein the sub gate insulating pattern has a dielectric constant between about 15 and about 20.

4. The thin film transistor array substrate as claimed in claim 1, wherein a dielectric constant of the main gate insulating film is between about 3 and about 4.

5. A thin film transistor array substrate, comprising:

a gate line;

a main gate insulating film formed over the gate line;

a data line formed on the main gate insulating film crossing the gate line such that the main gate insulating film is disposed between the gate line and the data line;

a thin film transistor provided at the intersection of the gate line and the data line, the transistor including a gate electrode extended from the gate line, a semiconductor pattern overlapping the gate electrode with the main gate insulating pattern disposed between the gate electrode and the semiconductor pattern, a source electrode connected to the data line, and a drain electrode connected to the semiconductor pattern at a portion separate from the source electrode;

a pixel electrode connected to the drain electrode of the thin film transistor; and

a sub gate insulating pattern disposed between the gate pattern and the main gate insulating film overlapping the gate pattern, the sub gate insulating pattern including a ferroelectric material,

wherein the sub gate insulating pattern is only on the gate pattern and contacts the gate pattern, and

wherein a dielectric constant of the sub gate insulating pattern is greater than a dielectric constant of the main gate insulating film,

wherein the sub gate insulating pattern includes any one of lead zirconate titanate, lead lanthanum titanate, barium magnesium fluoride, bismuth titanate, strontium bismuth titanate, and strontium bismuth titanate niobate.

6. The thin film transistor array substrate as claimed in claim 5, further comprising a protective film covering the thin film transistor and the data line, the protective film defining a hole at a portion of the drain electrode such that the pixel electrode is connected to the drain electrode through the hole.

7. The thin film transistor array substrate as claimed in claim 6, wherein the sub gate insulating pattern, the main gate insulating film and the protective film, and the pixel electrode are disposed over the gate line to define a storage capacitor.

8. The thin film transistor array substrate as claimed in claim 5, wherein a dielectric constant of the sub gate insulating pattern is between about 15 and about 20.

9. The thin film transistor array substrate as claimed in claim 5, wherein a dielectric constant of the main gate insulating film is between about 3 and about 4.