Nitride based LED with a p-type injection region
First Claim
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1. A semiconductor light emitting device, comprising:
- a semiconductor multilayer structure composed of a p-semiconductor layer, a quantum well emission layer, and an n-semiconductor layer each made of a nitride semiconductor and laminated in the stated order, light from the emission layer exiting through the n-semiconductor layer; and
a p-electrode facing and in electrical connection with the p-semiconductor layer, whereinthe p-semiconductor layer has, on a surface facing toward the p-electrode, (i) high-defect of dislocation-density regions in which defects of dislocation are localized and (ii) low-defect of dislocation-density regions, the high and low-defect of dislocation-density regions being at regularly or selectively distributed locations,the p-electrode has, on a surface facing toward the p-semiconductor layer, a plurality of projections or depressions that are distributed substantially uniformly, andthe p-electrode is directly in contact, at a top surface thereof, with the low-defect of dislocation-density regions of the p-semiconductor layer.
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Abstract
An LED chip (2) is composed of a p-GaN layer (10), an n-GaN layer (14), and an MQW emission layer (12) that is sandwiched between the GaN layers (10 and 14). Each layer is made of a GaN semiconductor. Light exits the LED chip (2) through the n-GaN layer (14). A p-electrode (16) of the LED chip (2) has a surface profile (24B) defined by a plurality of columnar projections (24A) formed in a uniformly distributed relation on the surface facing toward the p-GaN layer (10). The p-electrode (16) is in contact with the p-GaN layer (10) at the top surface of each projection (24A).
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Citations
17 Claims
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1. A semiconductor light emitting device, comprising:
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a semiconductor multilayer structure composed of a p-semiconductor layer, a quantum well emission layer, and an n-semiconductor layer each made of a nitride semiconductor and laminated in the stated order, light from the emission layer exiting through the n-semiconductor layer; and a p-electrode facing and in electrical connection with the p-semiconductor layer, wherein the p-semiconductor layer has, on a surface facing toward the p-electrode, (i) high-defect of dislocation-density regions in which defects of dislocation are localized and (ii) low-defect of dislocation-density regions, the high and low-defect of dislocation-density regions being at regularly or selectively distributed locations, the p-electrode has, on a surface facing toward the p-semiconductor layer, a plurality of projections or depressions that are distributed substantially uniformly, and the p-electrode is directly in contact, at a top surface thereof, with the low-defect of dislocation-density regions of the p-semiconductor layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Current AssigneeSignify Holding B.V. (Signify N.V.)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsNagai, Hideo
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Primary Examiner(s)Pert; Evan
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Assistant Examiner(s)Tran; Tan N
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Application NumberUS10/591,153Publication NumberTime in Patent Office1,266 DaysField of Search257/81, 257/95, 257/98, 257/99, 257/100US Class Current257/98CPC Class CodesH01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...H01L 33/0093 Wafer bonding; Removal of t...H01L 33/32 containing nitrogenH01L 33/385 the electrode extending at ...H01L 33/62 Arrangements for conducting...
