Stacked bit line dual word line nonvolatile memory

• US 7,420,242 B2
• Filed: 08/31/2005
• Issued: 09/02/2008
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang-Lan
• Primary Examiner(s): Lee; Calvin
• Application Number:
  US11/217,659
• Publication Number:
  US 20070045708A1
• Time in Patent Office: 1,098 Days
• Field of Search: 438128-131, 438/258, 438/600, 257/316, 257/530, 365/51, 365/103
• US Class Current: 257/316
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

Claims

1. An arrangement of nonvolatile memory devices, having a plurality of memory levels stacked level by level above a semiconductor substrate, each memory level comprising:

(a) an oxide disposed substantially above the semiconductor substrate;

(b) a plurality of word lines substantially disposed above the oxide layer;

(c) a plurality of bit lines substantially disposed above the oxide layer;

(d) an anti-fuse dielectric material substantially disposed on one or more sidewalls beside the bit lines and substantially in electrical contact with the bit lines, the anti-fuse dielectric material forming a plurality of side wall anti-fuse dielectrics beside the bit lines; and

(e) a plurality of via plugs substantially in electrical contact with the word lines and substantially in contact with the plurality of side wall anti-fuse dielectrics.

2. The arrangement of nonvolatile memory devices according to claim 1, wherein the word lines comprise pairs of word lines.

3. The arrangement of nonvolatile memory devices according to claim 1, wherein the bit lines are formed from polysilicon having a first type of background impurity and the via plugs are formed from polysilicon having a second type of background impurity opposite to the first type.

4. The arrangement of nonvolatile memory devices according to claim 3, wherein the first type of background impurity is N-type and the second type of background impurity is P-type.

5. The arrangement of nonvolatile memory devices according to claim 3, wherein the first type of background impurity is P-type and the second type of background impurity is N-type.

6. The arrangement of nonvolatile memory devices according to claim 4, wherein the word lines comprise pairs of word lines.

7. The arrangement of nonvolatile memory devices according to claim 1, wherein:

the word lines comprise pairs of word lines; and

the bit lines are formed from polysilicon having a first type of background impurity and the via plugs are formed from polysilicon having a second type of background impurity opposite to the first type.

8. The arrangement of nonvolatile memory devices according to claim 7, wherein the first type of background impurity is P-type and the second type of background impurity is N-type.

9. An arrangement of nonvolatile memory devices, comprising:

(a) a plurality of first word lines disposed within a first plane relative to a semiconductor substrate;

(b) a plurality of second word lines disposed within a second plane relative to the semiconductor substrate, wherein the second plane does not intersect the first plane;

(c) a plurality of bit lines orthogonally disposed relative to the first word lines and the second word lines, wherein each bit line is coupled to one of the first word lines and one of the second word lines;

(d) an anti-fuse dielectric material disposed on one or more sidewalls beside the bit lines and in electrical contact with the bit lines, the anti-fuse dielectric material forming a plurality of side wall anti-fuse dielectrics beside the bit lines; and

(e) a plurality of via plugs in electrical contact with the word lines and substantially in contact with the plurality of side wall anti-fuse dielectrics.

10. The arrangement of nonvolatile memory devices according to claim 9, wherein the word lines comprise pairs of word lines.

11. The arrangement of nonvolatile memory devices according to claim 9, wherein the bit lines are formed from polysilicon having a first type of background impurity and the via plugs are formed from polysilicon having a second type of background impurity opposite to the first type.

12. The arrangement of nonvolatile memory devices according to claim 11, wherein the first type of background impurity is N-type and the second type of background impurity is P-type.

13. The arrangement of nonvolatile memory devices according to claim 11, wherein the first type of background impurity is P-type and the second type of background impurity is N-type.