Post passivation structure for semiconductor chip or wafer

• US 7,420,276 B2
• Filed: 02/20/2004
• Issued: 09/02/2008
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): LOUIE, WAI SING
• Application Number:
  US10/783,195
• Publication Number:
  US 20040166659A1
• Time in Patent Office: 1,656 Days
• Field of Search: 257758-759, 257750-751, 257/771, 257/774, 257/762, 438637-638, 438/622, 438/624, 438/626, 438/631
• US Class Current: 257/758
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

Claims

1. A semiconductor chip connected to a wirebond interconnect, comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a first contact pad over said silicon substrate, wherein said first contact pad has a top surface with a first region and a second region, wherein said second region surrounds said first region;

a passivation layer over said metallization structure, over said dielectric layer and on said second region, wherein said passivation layer has a thickness greater than that of said dielectric layer, wherein a first opening in said passivation layer is over said first region and exposes said first region, wherein said first opening has a size between 0.1 and 50 micrometers, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;

a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region and exposes said first region, and wherein said polymer layer has a thickness between 2 and 50 μ

m, greater than that of said dielectric layer and greater than that of said passivation layer;

a second contact pad connected to said wirebond interconnect, wherein said second contact pad comprises an electroplated gold layer with a thickness between 2 and 100 μ

m, wherein said second contact pad is connected to said first contact pad through said first and second openings, and wherein the positions of said first and second contact pads from a top perspective view are different; and

a signal interconnect on said polymer layer, wherein said second contact pad is connected to said first contact pad through said signal interconnect.

2. The semiconductor chip of claim 1, wherein said second contact pad further comprises a titanium-containing layer under said electroplated gold layer.

3. The semiconductor chip of claim 2, wherein said titanium-containing layer comprises tungsten.

4. The semiconductor chip of claim 2, wherein said titanium-containing layer comprises nitrogen.

5. The semiconductor chip of claim 1, wherein said polymer layer comprises polyimide.

8. The semiconductor chip of claim 2, wherein said titanium-containing layer has a thickness between 0.01 and 3 μ

m.

9. The semiconductor chip of claim 2, wherein said second contact pad further comprises a seed layer between said titanium-containing layer and said electroplated gold layer, wherein said seed layer has a thickness between 0.05 and 3 μ

m.

6. A semiconductor chip connected to a wirebond interconnect, comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a first contact pad over said silicon substrate;

a passivation layer over said metallization structure and over said dielectric layer, wherein said passivation layer has a thickness greater than that of said dielectric layer, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;

a polymer layer on said passivation layer, wherein an opening in said polymer layer is over said first contact pad and exposes said first contact pad, and wherein said polymer layer has a thickness between 2 and 50 μ

m, greater than that of said dielectric layer and greater than that of said passivation layer;

a second contact pad connected to said wirebond interconnect, wherein said second contact pad comprises an electroplated gold layer with a thickness between 2 and 100 μ

m, wherein said second contact pad is connected to said first contact pad through said opening, and wherein the positions of said first and second contact pads from a top perspective view are different; and

a signal interconnect on said polymer layer, wherein said second contact pad is connected to said first contact pad through said signal interconnect.

10. The semiconductor chip of claim 6, wherein said second contact pad further comprises a titanium-containing layer under said electroplated gold layer.

11. The semiconductor chip of claim 10, wherein said titanium-containing layer has a thickness between 0.01 and 3 μ

m.

12. The semiconductor chip of claim 10, wherein said second contact pad further comprises a seed layer between said titanium-containing layer and said electroplated gold layer, wherein said seed layer has a thickness between 0.05 and 3 μ

m.

14. The semiconductor chip of claim 6, wherein said polymer layer comprises polyimide.

7. A semiconductor chip connected to a wirebond interconnect, comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a metallization structure over said semiconductor substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a first contact pad over said silicon substrate, wherein said first contact pad has a top surface with a first region and a second region, wherein said second region surrounds said first region;

a passivation layer over said metallization structure, over said dielectric layer and on said second region, wherein said passivation layer has a thickness greater than that of said dielectric layer, wherein a first opening in said passivation layer is over said first region and exposes said first region, wherein said first opening has a size between 0.1 and 50 micrometers, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;

a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region and exposes said first region, and wherein said polymer layer has a thickness between 2 and 50 μ

m, greater than that of said dielectric layer and greater than that of said passivation layer;

a second contact pad connected to said wirebond interconnect, wherein said second contact pad comprises a titanium-containing layer with a thickness between 0.01 and 3 μ

m, a seed layer with a thickness between 0.05 and 3 μ

m over said titanium-containing layer, and an electroplated gold layer with a thickness between 2 and 100 μ

m on said seed layer, wherein said second contact pad is connected to said first contact pad through said first and second openings, and wherein the positions of said first and second contact pads from a top perspective view are different; and

a signal interconnect on said polymer layer, wherein said second contact pad is connected to said first contact pad through said signal interconnect.

13. The semiconductor chip of claim 7, wherein said polymer layer comprises polyimide.