Latching input buffer circuit with variable hysteresis
First Claim
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1. A buffer circuit, comprising:
- a first buffer stage, the first buffer stage comprising;
a signal input;
a first node responsive to the signal input;
a second node responsive to the signal input;
a variable resistive device having a first terminal coupled to the first node and a second terminal coupled to the second node, the variable resistive device for providing a variable resistance between the first and second nodes;
a second buffer stage, the second buffer stage comprising;
a signal output;
a first transistor including a control electrode coupled to the first node;
a second transistor including a control electrode coupled to the second node;
a third transistor including a control electrode coupled to the first node;
a fourth transistor including a control electrode coupled to the second node;
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are series coupled transistors coupled between a first voltage terminal and a second voltage terminal.
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Abstract
An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes four series-coupled transistors. A first node is coupled to the control electrodes of two of the four transistors and the second node is coupled to the control electrodes of the other two transistors. The second stage includes a signal output. In some examples, a resistance provided by the resistive device is variable and provides the buffer circuit with hysteresis.
8 Citations
19 Claims
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1. A buffer circuit, comprising:
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a first buffer stage, the first buffer stage comprising; a signal input; a first node responsive to the signal input; a second node responsive to the signal input; a variable resistive device having a first terminal coupled to the first node and a second terminal coupled to the second node, the variable resistive device for providing a variable resistance between the first and second nodes; a second buffer stage, the second buffer stage comprising; a signal output; a first transistor including a control electrode coupled to the first node; a second transistor including a control electrode coupled to the second node; a third transistor including a control electrode coupled to the first node; a fourth transistor including a control electrode coupled to the second node; wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are series coupled transistors coupled between a first voltage terminal and a second voltage terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A buffer circuit comprising:
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a signal input; a first transistor including a control electrode connected to the signal input; a second transistor including a control electrode connected to the signal input; a first node connected to a first current terminal of the first transistor; a second node connected to a first current terminal of the second transistor; a resistive device coupled to provide a resistance between the first node and the second node; a third transistor including a control electrode connected to the first node; a fourth transistor including a control electrode connected to the second node; a fifth transistor including a control electrode connected to the first node; a sixth transistor including a control electrode connected to the second node; a signal output connected to a current electrode of the fourth transistor and a current electrode of the fifth transistor; wherein the third, fourth, fifth, and sixth transistors are coupled in series; wherein the third transistor and the fourth transistor are of a first conductivity type and the fifth transistor and sixth transistor of a second conductivity type opposite the first conductivity type. - View Dependent Claims (18)
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19. A buffer circuit, comprising:
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a first buffer stage, the first buffer stage comprising; a signal input; a first node responsive to the signal input; a second node responsive to the signal input; a resistive device coupled between the first node and the second node; a second buffer stage, the second buffer stage comprising; a signal output; a first transistor including a control electrode coupled to the first node; a second transistor including a control electrode coupled to the second node; a third transistor including a control electrode coupled to the first node; a fourth transistor including a control electrode coupled to the second node; wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are series coupled transistors coupled between a first voltage terminal and a second voltage terminal; a latch circuit coupled to the signal output to latch a state of the signal output; a tri-state circuit configured that when enabled, pulls a voltage level of the first node to a voltage level of the first voltage terminal and pulls a voltage level of the second node to a voltage level of the second voltage terminal; wherein the latch circuit is configured to retain the previous state of the signal output prior to the tri-state circuit being enabled.
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Specification