Multi-state memory having data recovery after program fail

• US 7,420,847 B2
• Filed: 12/14/2005
• Issued: 09/02/2008
• Est. Priority Date: 12/14/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Li, Yan
• Primary Examiner(s): Ho; Hoai V.
• Assistant Examiner(s): TRAN, ANTHAN
• Application Number:
  US11/304,960
• Publication Number:
  US 20060126394A1
• Time in Patent Office: 993 Days
• Field of Search: 365/185.22, 365/185.28, 365/185.09
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3413 Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A non-volatile memory device includes the ability to recover data in event of a program failure without having to maintain a copy of the data until the write is completed. As the integrity of the data can thus be maintained with having to save a copy, buffers can be freed up for other data or even eliminated, reducing the amount of controller space that needs to devoted data buffering. In exemplary embodiments, the data is recovered by logically combining the verify data for the (failed) write process maintained in data latches with the results of one or more read operations to reconstitute the data. The exemplary embodiments are for memory cells storing multi-state data, both in the format of independent upper page, lower page form, as well as in 2-bit form. This can be accomplished by a state machine and data latches in the sense amp area on the memory, without use of the controller.

Claims

1. A non-volatile memory, comprising:

a memory array having a plurality of non-volatile memory cells;

program circuitry selectively connectable to the memory cells for writing respective target data states thereto;

a set of data latches, one or more of which are connectable to each of the memory cells being written in a program operation to maintain verify data indicating whether the corresponding memory cell has been successfully written to the respective target data state;

sensing circuitry selectively connectable to the memory cells; and

logic circuitry that in response to an indication of a failed write operation for one or more memory cells combines the results of one or more read results from the sensing circuitry on said one or more memory cells with the corresponding verify data maintained in said memory latches to recover the respective target data state to which said memory cells were to have been programmed.

2. The memory of claim 1, wherein said non-volatile memory is part of a memory system including a controller and said non-volatile memory and said target data states are not maintained in said controller subsequent to performing a program operation write said target data to said memory cells.

3. The memory of claim 2, wherein said target data states are not maintained in the memory independently of said verify data.

4. The memory of claim 1, wherein said memory cells are multi-state memory cells.

5. The memory of claim 4, wherein said memory stores multi-state data in the memory cells in an upper page, lower page format and said target data is upper page target data.

6. The memory of claim 5, wherein said memory writes lower page data said memory cells prior to writing upper page target data to said memory cells.

7. The memory of claim 6, wherein sense circuitry reads lower page data into said data latches prior to writing the upper page target data to said memory cells.

8. The memory of claim 5, wherein said logic circuitry recovers both the lower page data and upper page target data.