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Multi-state memory having data recovery after program fail

  • US 7,420,847 B2
  • Filed: 12/14/2005
  • Issued: 09/02/2008
  • Est. Priority Date: 12/14/2004
  • Status: Active Grant
First Claim
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1. A non-volatile memory, comprising:

  • a memory array having a plurality of non-volatile memory cells;

    program circuitry selectively connectable to the memory cells for writing respective target data states thereto;

    a set of data latches, one or more of which are connectable to each of the memory cells being written in a program operation to maintain verify data indicating whether the corresponding memory cell has been successfully written to the respective target data state;

    sensing circuitry selectively connectable to the memory cells; and

    logic circuitry that in response to an indication of a failed write operation for one or more memory cells combines the results of one or more read results from the sensing circuitry on said one or more memory cells with the corresponding verify data maintained in said memory latches to recover the respective target data state to which said memory cells were to have been programmed.

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