Method, system, and circuit for operating a non-volatile memory array

• US 7,420,848 B2
• Filed: 01/09/2006
• Issued: 09/02/2008
• Est. Priority Date: 01/31/2002
• Status: Expired due to Term

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Shappir, Assaf, Avni, Dror
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US11/328,015
• Publication Number:
  US 20060126396A1
• Time in Patent Office: 967 Days
• Field of Search: 365/185.22
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

Claims

1. A control circuit for operating a set of memory cells in a memory array, said control circuit comprising:

a charge circuit adapted to produce a first operating pulse to a terminal of a first cell intended to place the first cell into a predefined state; and

a logic unit adapted to determine pulse characteristics of a second operating pulse as a function of the response of the first cell to the first operating pulse.

2. The control circuit according to claim 1, wherein said logic unit is further adapted to determine pulse characteristics of a third operating pulse as a function of the response of the first cell and a second cell to the first and second operating pulses, respectively.

3. The control circuit according to claim 1, wherein said logic unit is adapted to adjust the duration of said second operation pulse.

4. The control circuit according to claim 1, wherein said logic unit is adapted to adjust the amplitude of said second operation pulse.

5. The control circuit according to claim 1, further comprising a memory buffer adapted to store data received from the set of memory cells.

6. A system for operating a set of memory cells in a memory array, said system comprising:

a memory array;

a sense amplifier adapted to determine a response of operated cells; and

a control circuit adapted to produce a first operating pulse to a terminal of a first cell intended to place the first cell into a predefined state; and

adapted to determine pulse characteristics of a second operating pulse as a function of the response of the first cell to the first operating pulse.

7. The system according to claim 6, wherein said control circuit is further adapted to determine pulse characteristics of a third operating pulse as a function of the response of the first cell and a second cell to the first and second operating pulses, respectively.

8. The system according to claim 6, wherein said control circuit is adapted to adjust the duration of said second operation pulse.

9. The system according to claim 6, wherein said control circuit is adapted to adjust the amplitude of said second operation pulse.