Semiconductor integrated circuit and leak current reducing method
First Claim
1. A semiconductor integrated circuit device comprising at least:
- an SRAM memory cell array comprising a plurality memory cells each including load MOS transistors; and
a substrate bias generating circuit which is electrically connected to the load MOS transistors and supplies a first substrate potential to the load MOS transistors upon at least operation and standby of the SRAM memory cell array in such a manner that absolute values of threshold voltages of the load MOS transistors increase.
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Accused Products
Abstract
The present invention provides a semiconductor integrated circuit device which includes at least an SRAM memory cell array comprising a plurality of memory cells each constituted of a circuit including load MOS transistors, drive MOS transistors and transfer MOS transistors, a substrate bias generating circuit which is electrically connected to the load MOS transistors and supplies a substrate potential to the load MOS transistors during at least operation and standby, and a source bias generating circuit which is electrically connected to the drive MOS transistors and supplies a source potential to the drive MOS transistors at standby. It is possible to reduce a leak current in an SRAM memory cell during both operation and standby and reduce current consumption.
25 Citations
25 Claims
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1. A semiconductor integrated circuit device comprising at least:
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an SRAM memory cell array comprising a plurality memory cells each including load MOS transistors; and a substrate bias generating circuit which is electrically connected to the load MOS transistors and supplies a first substrate potential to the load MOS transistors upon at least operation and standby of the SRAM memory cell array in such a manner that absolute values of threshold voltages of the load MOS transistors increase. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A leak current reducing method for an SRAM memory cell, comprising the steps of:
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generating a first substrate potential for increasing absolute values of threshold voltages of load MOS transistors included in the SRAM memory cell; and supplying the first substrate potential to the load MOS transistors upon at least operation and standby of the SRAM memory cell. - View Dependent Claims (22, 23, 24, 25)
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Specification