Adaptive-allocation of I/O bandwidth using a configurable interconnect topology

• US 7,420,990 B2
• Filed: 11/10/2006
• Issued: 09/02/2008
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ching, Michael, Woo, Steven
• Primary Examiner(s): Nguyen; Brian D
• Application Number:
  US11/558,757
• Publication Number:
  US 20070071032A1
• Time in Patent Office: 662 Days
• Field of Search: 370/468, 370/419, 370/463
• US Class Current: 370/468
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0294 Provision for current-mode coupling
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04L 5/143 for modulated signals H04L5/1469 takes precedence
• CPC Class Codes: H04L 5/18 Automatic changing of the traffic direction
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bidirectional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

Claims

1. A system comprising:

a first integrated circuit having a first interface coupled to a first signal path, the first interface having a first plurality of contacts;

a second integrated circuit having a second interface coupled to the first signal path, the second interface having a second plurality of contacts;

wherein the first and second integrated circuits are operable in a first and second mode of operation, wherein;

during the first mode of operation, the first integrated circuit configures a first set of contacts in the first plurality of contacts to output and receive signals, the second integrated circuit configures a second set of contacts in the second plurality of contacts to output and receive signals to and from the first set of contacts, the first and second integrated circuits configure the first and second sets of contacts in response to a control signal; and

during the second mode of operation, the first integrated circuit configures a third set of contacts in the first plurality of contacts to output signals, the second integrated circuit configures a fourth set of contacts in the second plurality of contacts to receive the signals from the third set of contacts; and

a control circuit to output the control signal;

wherein the control signal is output in response to an indication as to a number of transmit commands.

2. The system of claim 1, wherein the indication includes a request for bandwidth.

3. The system of claim 1, wherein the control circuit includes a register to output the control signal.

4. The system of claim 1, wherein the control circuit outputs the control signal in response to executable instructions.

5. A system comprising:

a first integrated circuit having a first interface coupled to a first signal path, the first interface having a first plurality of contacts;

a second integrated circuit having a second interface coupled to the first signal path, the second interface having a second plurality of contacts;

wherein the first and second integrated circuits are operable in a first and second mode of operation, wherein;

during the first mode of operation, the first integrated circuit configures a first set of contacts in the first plurality of contacts to output and receive signals, the second integrated circuit configures a second set of contacts in the second plurality of contacts to output and receive signals to and from the first set of contacts, the first and second integrated circuits configure the first and second sets of contacts in response to a control signal; and

during the second mode of operation, the first integrated circuit configures a third set of contacts in the first plurality of contacts to output signals, the second integrated circuit configures a fourth set of contacts in the second plurality of contacts to receive the signals from the third set of contacts; and

a control circuit to output the control signal;

wherein the control signal is output in response to an indication as to a number of receive commands.

6. A system comprising:

a first integrated circuit having a first interface coupled to a first signal path, the first interface having a first plurality of contacts;

a second integrated circuit having a second interface coupled to the first signal path, the second interface having a second plurality of contacts;

wherein the first and second integrated circuits are operable in a first and second mode of operation, wherein;

during the first mode of operation, the first integrated circuit configures a first set of contacts in the first plurality of contacts to output and receive signals, the second integrated circuit configures a second set of contacts in the second plurality of contacts to output and receive signals to and from the first set of contacts, the first and second integrated circuits configure the first and second sets of contacts in response to a control signal; and

during the second mode of operation, the first integrated circuit configures a third set of contacts in the first plurality of contacts to output signals, the second integrated circuit configures a fourth set of contacts in the second plurality of contacts to receive the signals from the third set of contacts; and

a control circuit to output the control signal;

wherein the control signal is output in response to an average time a data packet waits.

7. A system comprising:

a first integrated circuit having a first interface;

a second integrated circuit having a second interface;

wherein the first and second integrated circuits are operable in a first and second mode of operation, wherein;

during the first mode of operation, the first interface is configured to transfer bidirectional signals between the first and second interfaces and the second interface is configured to transfer bidirectional signals between the first and second interfaces, wherein the first and second integrated circuits operate in response to a control signal; and

during the second mode of operation, a portion of the first interface is configured to output unidirectional signals and a portion of the second interface is configured to receive the unidirectional signals from the first portion; and

a control logic to output the control signal;

wherein the control signal is output in response to an indication as to the amount of data to be transferred between the first and second integrated circuits during a period of time.

8. The system of claim 7, wherein the first integrated circuit is included in a memory controller and the second integrated circuit is included in an integrated circuit memory device.

9. The system of claim 8, wherein the integrated circuit memory device is disposed on a memory module.

10. The system of claim 8, wherein the control signal is a memory command output by the memory controller.

11. The system of claim 8, wherein the first and second interfaces include a first and second transceiver, the first and second transceivers each include a transmit and receive circuit coupled to a serializer circuit and deserializer circuit.

12. The system of claim 8, wherein the control logic is included in the first integrated circuit.

13. The system of claim 12, wherein the control logic includes a register to output the control signal.

14. A method of operation in a system including a first integrated circuit having a first interface and a second integrated circuit having a second interface, the method comprising:

configuring the first interface to transfer bidirectional signals between the first interface and the second interface;

configuring the second interface to transfer bidirectional signals between the first interface and the second interface;

outputting a control signal that indicates an amount of data to be transferred between the first and second integrated circuits;

reconfiguring a portion of the first interface to output unidirectional signals to a portion of the second interface in response to the control signal; and

reconfiguring the portion of the second interface to receive unidirectional signals from the portion of the first interface in response to the control signal,

wherein the control signal is output in response to a number of transmit commands.

15. The method of claim 14, wherein the control signal is output in response to a request for bandwidth.

16. A method of operation in a system including a first integrated circuit having a first interface and a second integrated circuit having a second interface, the method comprising:

configuring the first interface to transfer bidirectional signals between the first interface and the second interface, the first interface having first and second portions;

configuring the second interface to transfer bidirectional signals between the first interface and the second interface, the second interface having first and second portions;

outputting a control signal that indicates an amount of data to be transferred between the first and second integrated circuits;

reconfiguring the first portion of the first interface to output unidirectional signals to the first portion of the second interface in response to the control signal; and

reconfiguring the second portion of the second interface to receive unidirectional signals from the second portion of the first interface in response to the control signal,

wherein the control signal is output in response to a number of receive commands.

17. A method of operation in a system including a first integrated circuit having a first interface and a second integrated circuit having a second interface, the method comprising:

configuring the first interface to transfer bidirectional signals between the first interface and the second interface, the first interface having first and second portions;

configuring the second interface to transfer bidirectional signals between the first interface and the second interface, the second interface having first and second portions;

outputting a control signal that indicates an amount of data to be transferred between the first and second integrated circuits;

reconfiguring the first portion of the first interface to output unidirectional signals to the first portion of the second interface in response to the control signal; and

reconfiguring the second portion of the second interface to receive unidirectional signals from the second portion of the first interface in response to the control signal,

wherein the control signal is output in response to an average time a data packet waits in the first integrated circuit.