Transformer isolator for digital power supply

• US 7,421,028 B2
• Filed: 06/03/2004
• Issued: 09/02/2008
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Dupuis, Timothy
• Primary Examiner(s): Ahn; Sam K.
• Application Number:
  US10/860,399
• Publication Number:
  US 20050271147A1
• Time in Patent Office: 1,552 Days
• Field of Search: 375/257, 375/258, 438/197, 438/270, 438/288, 438/335, 327/177, 327/304, 327/382, 327/565, 379/399.01, 379/93.05, 379/93.06, 379/93.29
• US Class Current: 375/258
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop

Abstract

A system for providing voltage isolation includes the first and second chips, each containing functional circuitry. The chips are interconnected via at least one RF isolation link that provides voltage isolation between the first chip and the second chip.

Claims

1. A system for providing voltage isolation, comprising:

a first chip containing functional circuitry;

a second chip containing functional circuitry;

at least one RF isolation link interconnecting the first and the second chip, the RF isolation link providing voltage isolation between the first chip and the second chip, wherein the RF isolation link further comprises;

a first transformer on the first chip;

a second transformer on the second chip;

a transmitter associated with the first transformer for transmitting an RF carrier onto the RF isolation link;

a receiver associated with the second transformer for receiving an RF carrier onto the RF isolation link.

2. The system of claim 1, wherein the at least one RF isolation link is integrated on the first chip and the second chip.

3. The system of claim 1,

wherein the transmitter is responsive to a logical data signal and the RF carrier for generating a transmitter output.

4. The system of claim 3, wherein the transmitter outputs the RF carrier as the transmitter output responsive to a logical “

1”

logical data signal.

5. The system of claim 3 wherein the transmitter shuts down the RF carrier as the transmitter output responsive to a logical “

0”

logical data signal.

6. The system of claim 3, wherein the presence of the RF carrier signal indicates a received logical “

1” and

the absence of the RF carrier signal indicates a logical “

0”

.

7. The system of claim 1, wherein the at least one RF isolation link transmits data between the first and the second chip using amplitude modulation.

8. The system of claim 1, wherein the at least one RF isolation link transmits data between the first and the second chip using frequency modulation.

9. The system of claim 1, further including a microcontroller in the first chip coupled to the at least one RF isolation link.

10. The system of claim 9, further including:

a digital to analog convertor in the second chip for converting digital signals from the microcontroller into an analog output; and

an analog to digital convertor in the second chip for converting analog signals from an input into a digital signal for the microcontroller.

11. A system for providing voltage isolation, comprising:

a first chip containing functional circuitry;

a second chip containing functional circuitry; and

at least one RF isolation link interconnecting the first and the second chip, the RF isolation link providing voltage isolation between the first chip and the second clip, wherein the RF isolation link further comprises;

a first transformer on the first chip;

a second transformer on the second chip;

a first transceiver circuitry associated with the first transformer for transmitting and receiving an RF carrier onto the at least one RF isolation link;

second transceiver circuitry associated with the second transformer for transmitting and receiving an RF carrier onto the at least one RF isolation link.

12. An apparatus for providing voltage isolation, comprising:

a chip containing functional circuitry; and

a portion of at least one RF isolation link interconnecting the chip with an external chip and the second chip, the RF isolation link providing voltage isolation between the chip and the external chip, wherein the portion of the at least one RF isolation link comprises;

a transmitter responsive to a logical data signal and an RF carrier signal for generating a transmitter output; and

an integrated transformer for electromagnetically coupling the transmitter output onto an external link providing a connection to a second integrated transformer and associated receiver on a second chip.

13. The apparatus of claim 12, wherein the transmitter outputs the RF carrier as the transmitter output responsive to a logical “

1”

logical data signal.

14. The apparatus of claim 13, wherein the transmitter shuts down the RF carrier as the transmitter output responsive to a logical “

0”

logical data signal.

15. The apparatus of claim 12, wherein the receiver further comprises:

an amplifier stage for amplifying the signal on the external link;

a detector coupled to the amplifier stage for detecting the presence or absence of the RF carrier signal in an amplified transmitter output from the amplifier stage.

16. The apparatus of claim 15, wherein the presence of the RF carrier signal indicates a received logical “

1” and

the absence of the RF carrier signal indicates a logical“

0”

.

17. The apparatus of claim 12, wherein the at least one RF isolation link transmits data between the chip and the external chip using amplitude modulation.

18. The apparatus of claim 12, wherein the at least one RF isolation link transmits data between the chip and the external chip using frequency modulation.

19. The apparatus of claim 12, further including a microcontroller in the chip coupled to the at least one RF isolation link.

20. A system for providing voltage isolation, comprising:

a first chip containing functional circuitry, said first chip including;

a first transmitter responsive to a logical data signal and an RF carrier signal for generating a transmitter output, wherein the transmitter outputs the RF carrier as the transmitter output responsive to a logical “

1”

logical data signal and shuts down the RF carrier as the transmitter output responsive to a logical “

0”

logical data signal;

a first amplifier stage for amplifying a received signal;

a first detector coupled to the amplifier stage for detecting the presence or absence of the RF carrier signal in an amplified received signal from the amplifier stage, wherein the presence of the RF carrier signal indicates a received logical “

1” and

the absence of the RF carrier signal indicates a logical “

0;

”

a first transformer for electromagnetically coupling the transmitter to an external link and for electromagnetically coupling the external link to the amplifier stage;

a second chip containing functional circuitry;

a second transmitter responsive to a logical data signal and an RF carrier signal for generating a transmitter output, wherein the transmitter outputs the RF carrier as the transmitter output responsive to a logical “

1”

logical data signal and shuts down the RE carrier as the transmitter output responsive to a logical “

0”

logical data signal;

a second amplifier stage for amplifying a received signal;

a second detector coupled to the amplifier stage for detecting the presence or absence of the RF carrier signal in an amplified received signal from the amplifier stage, wherein the presence of the RF carrier signal indicates a received logical “

1” and

the absence of the RF carrier signal indicates a logical “

0;

”

a second transformer for electromagnetically coupling the transmitter to an external link and for electromagnetically coupling the external link to the amplifier stage; and

wherein the first transformer and the second transformer provide voltage isolation between the first chip and the second chip.

21. The system of claim 20, wherein the RF carrier is amplitude modulation.

22. The system of claim 20, wherein the RF carrier is frequency modulation.

23. A system for providing voltage isolation, comprising:

a chip containing functional circuitry, said first chip including;

a transmitter responsive to a logical data signal and an RF carrier signal for generating a transmitter output, wherein the transmitter outputs the RF carrier as the transmitter output responsive to a logical “

1”

logical data signal and shuts down the RF carrier as the transmitter output responsive to a logical “

0”

logical data signal;

a first transformer for electromagnetically coupling the transmitter to an external link;

a second chip containing functional circuitry;

an amplifier stage for amplifying a received signal on the external link;

a receiver coupled to the amplifier stage for detecting the presence or absence of the RF carrier signal in an amplified received signal from the amplifier stage, wherein the presence of the RF carrier signal indicates a received logical “

1” and

the absence of the RF carrier signal indicates a logical “

0;

”

a second transformer for electromagnetically coupling the received signal on the external link to the amplifier stage; and

wherein the first transformer and the second transformer provide voltage isolation between the first chip and the second chip.

24. The system of claim 23, wherein the RF carrier is amplitude modulation.

25. The system of claim 23, wherein the RF carrier is frequency modulation.

26. A system of a circuit package, comprising:

a first die containing functional circuitry;

a second die containing functional circuitry; and

at least one RF isolation link interconnecting the first and the second die, the RF isolation link providing voltage isolation between the first die and the second die, wherein the RF isolation link further comprises;

a first transformer on the first die;

a second transformer on the second die;

a transmitter associated with the first transformer for transmitting an RF carrier onto the RF isolation link;

a receiver associated with the second transformer for receiving an RF carrier onto the RF isolation link.

27. The system of claim 26,

wherein the transmitter responsive to a logical data signal and the RF carrier signal for generating a transmitter output.

28. The system of claim 27, wherein the transmitter outputs the RF carrier as the transmitter output responsive to a logical “

1”

logical data signal.

29. The system of claim 28, wherein the transmitter shuts down the RF carrier as the transmitter output responsive to a logical “

0”

logical data signal.

30. The system of claim 26, wherein the presence of the RF carrier signal indicates a received logical “

1” and

the absence of the RF carrier signal indicates a logical “

0”

.

31. The system of claim 26, wherein the at least one RF isolation link transmits data between the first and the second die using amplitude modulation.

32. The system of claim 26, wherein the at least one RF isolation link transmits data between the first and the second die using frequency modulation.

33. The system of claim 26, further including:

a digital input coupled to the first die; and

a digital output coupled to the second die.

34. The system of claim 26, further including:

a digital input/output coupled to the first die; and

an analog input/output coupled to the second die.

35. A circuit package, comprising:

a first die containing functional circuitry;

a second die containing functional circuitry; and

at least one RF isolation link interconnecting the first and the second die, the RF isolation link providing voltage isolation between the first die and the second die, wherein the RF isolation link further comprises;

a first transformer on the first chip;

a second transformer on the second chip;

first transceiver circuitry associated with the first transformer for transmitting and receiving an RF carrier onto the at least one RF isolation link;

second transceiver circuitry associated with the second transformer for transmitting and receiving an RF carrier onto the at least one RF isolation link.

36. An integrated circuit with high voltage isolation interface, comprising:

a semiconductor substrate;

a functional circuit integrally formed on said substrate for processing at least a single bit of digital data;

an isolator integrally formed on said substrate for interfacing with said functional circuit for allowing external data from a potentially high voltage circuit relative to said functional circuit to be input across said isolator to said functional circuit or for allowing data to be output from said functional circuit across said isolator to said potentially high voltage circuit, wherein said isolator comprises;

a first conductive element formed on said semiconductor substrate and conducively interfaced with said functional circuit;

a second conductive element formed on said semiconductor substrate and providing a conductive interface to the exterior of said semiconductor substrate; and

said first conductive element electrically isolated from said second conductive element to allow only electromagnetic coupling there between, such that a portion of the electromagnetic spectral energy can be coupled there across.

37. The integrated circuit of claim 36, wherein said first conductive element is electrically isolated from said second conductive element by a layer of insulating material.

38. The integrated circuit of claim 37, wherein said insulating material comprises silicon dioxide.

39. The integrated circuit of claim 38, wherein said first conductive element and said second conductive element are fabricated from metal layers utilized in the fabrication of said functional circuit.

40. The integrated circuit of claim 36, wherein said functional circuit is formed on said semiconductor substrate in an area separate from said isolator.

41. The integrated circuit of claim 36, wherein said functional circuit is operable to operate in either a data receive mode or a data transmission mode.

42. The integrated circuit of claim 41, wherein said functional circuit includes a driver for driving said first conductive element in the data transmission mode.

43. The integrated circuit of claim 42, wherein said isolator operates over a finite bandwidth and said driver is operable to drive said first conductive element such that the spectral energy output thereby is concentrated substantially within said bandwidth.

44. The integrated circuit of claim 43, wherein said driver is operable to modulate the spectral energy output thereby with the data to be transmitted.

45. The integrated circuit of claim 44, wherein said modulation comprises providing an output for one data state and not providing an output for the other data state in a binary system.

46. The integrated circuit of claim 43, wherein said first conductive element has an impedance that has an inductive element associated therewith.

47. The integrated circuit of claim 46, wherein said first inductive element comprises a primary coil formed on one layer of said semiconductor substrate and said second inductive element comprises a secondary coil formed on a second layer of said semiconductor substrate and separated therefrom by a layer of dielectric.

48. The integrated circuit of claim 36, wherein said first inductive element comprises a primary coil formed on one layer of said semiconductor substrate and said second inductive element comprises a secondary coil formed on a second layer of said semiconductor substrate and separated therefrom by a layer of dielectric.

49. The integrated circuit of claim 48, wherein said isolator is disposed on a portion of said semiconductor substrate not overlying said functional circuit.