Checks for signal lines

• US 7,421,672 B2
• Filed: 07/12/2006
• Issued: 09/02/2008
• Est. Priority Date: 06/18/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sun, Ping, McRonald, Andrew, Meyer, Neal, Neal, Brett, Genz, Lee, Garrison, Gene
• Primary Examiner(s): Dinh; Paul
• Assistant Examiner(s): Parihar; Suchin
• Application Number:
  US11/485,154
• Publication Number:
  US 20060253817A1
• Time in Patent Office: 783 Days
• Field of Search: 716/5, 716/1, 716/14
• US Class Current: 716/106
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline and a segment of the second polyline is within a first tolerance, determination, if the distance is not within the first tolerance, of whether the distance is within a second tolerance, determination, if the distance is not within the first tolerance and is within the second tolerance, of whether the length of the segment of the first polyline is less than a first threshold, and to indicate that the first polyline and the second polyline are sufficiently spaced, if the distance is not within the first tolerance and is within the second tolerance, and if the length of the segment of the first polyline is less than the first threshold.

Claims

1. A method comprising:

identifying a net;

identifying a segment of the net;

determining a minimum channel spacing for the segment, wherein the minimum channel spacing is based on X=(R²−

Z²)^1/2, where X is the minimum channel spacing, R is a minimum radial spacing associated with the identified segment, and Z is a thickness of an adjacent dielectric layer;

defining a polygon based on the segment and on the minimum channel spacing;

identifying segments of other nets that are overlapped by the polygon; and

for at least one of the other nets, determining a cumulative parallel length between the subject segment and the identified segments.

2. A method according to claim 1, wherein defining the polygon comprises:

defining a capless polygon to outline the segment; and

expanding a width of the capless polygon based on the minimum channel spacing.

3. A method according to claim 2, further comprising:

repeating the method for each other segment of the net.

4. A method according to claim 1, further comprising:

for the at least one of the other nets, marking the identified segments as violating a design rule if the cumulative parallel length is greater than a maximum allowable length.

5. A storage device storing processor-executable code, which when executed by a computer system causes the computer to execute code for checking a circuit layout, the code comprising:

code to identify a net;

code to identify a segment of the net;

code to determine a minimum channel spacing for the segment, wherein the minimum channel spacing is based on X=(R²−

Z²)^1/2, where X is the minimum channel spacing, R is a minimum radial spacing associated with the identified segment, and Z is a thickness of an adjacent dielectric layer;

code to define a polygon based on the segment and on the minimum channel spacing;

code to identify segments of other nets that are overlapped by the polygon; and

code to determine, for at least one of the other nets, a cumulative parallel length between the subject segment and the identified segments.

6. A medium according to claim 5, wherein the code to define the polygon comprises:

code to define a capless polygon to circumscribe the segment; and

code to expand a width of the capless polygon based on the minimum channel spacing.

7. A medium according to claim 6, the code further comprising:

code to repeat the method for each other segment of the net.

8. A medium according to claim 5, the code further comprising:

code to mark, for the at least one of the other nets, the identified segments as violating a design rule if the cumulative parallel length is greater than a maximum allowable length.