High performance system-on-chip using post passivation process

• US 7,422,941 B2
• Filed: 10/23/2007
• Issued: 09/09/2008
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US11/877,647
• Publication Number:
  US 20080044976A1
• Time in Patent Office: 322 Days
• Field of Search: 438/238, 438/381, 438618-646, 257/E21.022
• US Class Current: 438/238
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/642 : Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/647 : Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 257/92 : Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Abstract

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Claims

1. A method of forming an integrated circuit chip, comprising:

providing a silicon substrate, multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises electroplated copper, a second dielectric layer between said first and second metal layers, and a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip;

forming a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers, greater than that of said passivation layer, greater than that of said first dielectric layer and greater than that of said second dielectric layer, and wherein said forming said first polymer layer comprises a coating process and a curing process;

forming a coil and a metal line on said first polymer layer, wherein said forming said coil comprises an electroplating process, wherein said coil has a thickness greater than that of said first metal layer and greater than that of said second metal layer, wherein said metal line has a thickness greater than that of said first metal layer and greater than that of said second metal layer, and wherein said metal line and said coil are separate from each other; and

forming a second polymer layer over said metal line.

2. The method of claim 1, wherein said forming said coil comprises a gold electroplating process.

3. The method of claim 1, wherein said forming said coil comprises a copper electroplating process.

4. The method of claim 1, wherein said forming said first polymer layer comprises forming a polyimide layer over said passivation layer.

5. The method of claim 1, wherein said forming said first polymer layer comprises forming a benzocyclobutene (BCB) layer over said passivation layer.

6. The method of claim 1, wherein said passivation layer further comprises an oxide layer under said topmost nitride layer of said integrated circuit chip.

7. The method of claim 1 further comprising providing a third metal layer over said passivation layer, wherein said third metal layer has a thickness between 0.2 and 5 micrometers, followed by said forming said first polymer layer further over said third metal layer.

8. A method of forming an integrated circuit chip, comprising:

providing a silicon substrate, multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises electroplated copper, a second dielectric layer between said first and second metal layers, and an insulating, separating layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said insulating, separating layer is over a first pad of said metallization structure and exposes said first pad, and a second opening in said insulating, separating layer is over a second pad of said metallization structure and exposes said second pad, wherein said first and second pads are separate from each other, and wherein said insulating, separating layer comprises a passivation layer over said metallization structure and over said first and second dielectric layers, and a first polymer layer on said passivation layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip, wherein said first polymer layer has a thickness between 2 and 150 micrometers, greater than that of said passivation layer, greater than that of said first dielectric layer and greater than that of said second dielectric layer, and wherein said first polymer layer is formed by a process comprising a coating process and a curing process;

forming a coil and a metal line on said insulating, separating layer, wherein said coil is connected to said first pad through said first opening, wherein said forming said coil comprises a copper electroplating process, wherein said coil has a thickness greater than that of said first metal layer and greater than that of said second metal layer, wherein said metal line is connected to said second pad through said second opening, wherein said metal line has a thickness greater than that of said first metal layer and greater than that of said second metal layer, and wherein said metal line and said coil are separate from each other; and

forming a second polymer layer over said metal line.

9. The method of claim 8, wherein said first polymer layer comprises polyimide.

10. The method of claim 8, wherein said first polymer layer comprises benzocyclobutene (BCB).

11. The method of claim 8, wherein said passivation layer further comprises an oxide layer under said topmost nitride layer of said integrated circuit chip.

12. The method of claim 8, wherein said second opening has a transverse dimension between 0.5 and 30 micrometers.

13. The method of claim 8, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers.

14. The method of claim 8, wherein said metal line comprises a power connection.

15. The method of claim 8, wherein said metal line comprises a ground connection.

16. The method of claim 8, wherein said metal line comprises a signal connection.

17. A method of forming an integrated circuit chip, comprising:

providing a silicon substrate, multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises a topmost sub-micron integrated circuit of said integrated circuit chip, and wherein said metallization structure comprises electroplated copper, a second dielectric layer between said first and second metal layers, and a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a nitride layer;

forming a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers, greater than that of said passivation layer, greater than that of said first dielectric layer and greater than that of said second dielectric layer, and wherein said forming said first polymer layer comprises a coating process and a curing process;

forming a coil and a metal line on said first polymer layer, wherein said forming said coil comprises forming a gold layer over said first polymer layer, wherein said coil has a thickness greater than that of said first metal layer and greater than that of said second metal layer, wherein said metal line has a thickness greater than that of said first metal layer and greater than that of said second metal layer, and wherein said metal line and said coil are separate from each other; and

forming a second polymer layer over said metal line.

18. The method of claim 17, wherein said forming said first polymer layer comprises forming a polyimide layer over said passivation layer.

19. The method of claim 17, wherein said forming said first polymer layer comprises forming a benzocyclobutene (BCB) layer over said passivation layer.

20. The method of claim 17, wherein said passivation layer further comprises an oxide layer under said nitride layer.

21. The method of claim 17 further comprising providing a third metal layer over said passivation layer, wherein said third metal layer has a thickness between 0.2 and 5 micrometers, followed by said forming said first polymer layer further over said third metal layer.

22. The method of claim 17, wherein an opening in said passivation layer exposes a metal pad of said metallization structure and is over said metal pad, wherein said coil is connected to said metal pad through said opening, and wherein said opening has a transverse dimension between 0.5 and 30 micrometers.

23. The method of claim 17, wherein said forming said gold layer comprises an electroplating process.

24. The method of claim 17, wherein said forming said gold layer comprises a sputter process.

25. The method of claim 17, wherein said metal line comprises a ground connection.