Strain-silicon CMOS using etch-stop layer and method of manufacture

• US 7,423,283 B1
• Filed: 06/07/2005
• Issued: 09/09/2008
• Est. Priority Date: 06/07/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Nayak, Deepak Kumar, Luo, Yuhao
• Primary Examiner(s): Nhu; David
• Application Number:
  US11/146,640
• Time in Patent Office: 1,190 Days
• Field of Search: 257/19, 257/18, 257/20, 257/24, 257/55, 257/63, 257/29, 257/347
• US Class Current: 257/19
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide strain in the plane of the channel region. In a particular embodiment, a tensile silicon nitride layer is formed over recesses of an NMOS transistor in a CMOS cell, and a compressive silicon nitride layer is formed over recesses of a PMOS transistor in the CMOS cell. In a particular embodiment the stressed silicon nitride layer(s) is a chemical etch stop layer.

Claims

1. A semiconductor structure comprising a transistor, the transistor comprising:

a drain region;

a source region;

a gate;

a first sidewall spacer on a first side of the gate;

a second sidewall spacer on a second side of the gate;

a channel region between the drain region and the source region, a top of the channel region being proximate to a gate dielectric layer;

a first recess formed in the drain region below the top of the channel region;

a second recess formed in the source region below the top of the channel region;

an ohmic contact layer formed in the first recess and in the second recess; and

a stressed silicon nitride layer formed over the ohmic contact layer in at least a portion of the first recess below the top of the channel region proximate to the first sidewall spacer and in at least a portion of the second recess below the top of the channel region proximate to the second sidewall spacer.

2. The semiconductor structure of claim 1 wherein the stressed silicon nitride layer extends from a first isolation dielectric across the drain region, gate and source region to a second isolation dielectric.

3. The semiconductor structure of claim 1 wherein the stressed silicon nitride layer is a chemical etch stop layer.

4. The semiconductor structure of claim 1 wherein the stressed silicon nitride layer fills the first recess and the second recess.

5. The semiconductor structure of claim 1 wherein the transistor is a PMOS transistor and the stressed silicon nitride layer is a compressive silicon nitride layer.

6. The semiconductor structure of claim 1 wherein the transistor is an NMOS transistor and the stressed silicon nitride layer is a tensile silicon nitride layer.

7. The semiconductor structure of claim 1 wherein the first recess is aligned to the first sidewall spacer and the second recess is aligned to the second sidewall spacer.

8. The semiconductor structure of claim 1 further comprising a stressed inter-metal dielectric (“

IMD”

) layer formed over the stressed silicon nitride layer.

9. The semiconductor structure of claim 1 wherein the transistor comprises a portion of a complementary metal-oxide-semiconductor (“

CMOS”

) cell and the stressed silicon nitride layer has a first type of stress, and further comprising a second transistor, the second transistor having

a second drain region;

a second source region;

a second gate;

a third sidewall spacer on a first side of the second gate;

a fourth sidewall spacer on a second side of the second gate;

a second channel region between the second drain region and the second source region;

a third recess formed in the second drain region;

a fourth recess formed in the second source region, the ohmic contact layer being further formed in the third recess and in the fourth recess; and

a second stressed silicon nitride layer having a second type of stress formed over the ohmic contact layer in at least a portion of the third recess proximate to the third sidewall spacer and in at least a portion of the fourth recess proximate to the fourth sidewall spacer.

10. The semiconductor structure of claim 9 wherein the stressed silicon nitride layer and the second stressed silicon nitride layer overlie a dielectric-filled isolation trench disposed between the transistor and the second transistor.

11. The semiconductor structure of claim 9 wherein at least one layer selected from the group consisting of the stressed silicon nitride layer and the second stressed silicon nitride layer is patterned according to a well mask.

12. A semiconductor structure comprising a transistor, the transistor comprising:

a drain region;

a source region;

a gate;

a first sidewall spacer on a first side of the gate;

a second sidewall spacer on a second side of the gate;

a channel region between the drain region and the source region;

a first recess formed in the drain region;

a second recess formed in the source region;

an ohmic contact layer formed in the first recess and in the second recess;

a first stressed silicon nitride layer formed over the ohmic contact layer in at least a portion of the first recess proximate to the first sidewall spacer and in at least a portion of the second recess proximate to the second sidewall spacer;

wherein the transistor comprises a portion of a complementary metal-oxide-semiconductor (“

CMOS”

) cell and the first stressed silicon nitride layer has a first type of stress, and further comprising a second transistor, the second transistor having

a second drain region;

a second source region;

a second gate;

a third sidewall spacer on a first side of the second gate;

a fourth sidewall spacer on a second side of the second gate;

a second channel region between the second drain region and the second source region;

a third recess formed in the second drain region;

a fourth recess formed in the second source region, the ohmic contact layer being further formed in the third recess and in the fourth recess; and

a second stressed silicon nitride layer having a second type of stress formed over the ohmic contact layer in at least a portion of the third recess proximate to the third sidewall spacer and in at least a portion of the fourth recess proximate to the fourth sidewall spacer.

13. The semiconductor structure of claim 12 wherein the first stressed silicon nitride layer and the second stressed silicon nitride layer overlie a dielectric-filled isolation trench disposed between the transistor and the second transistor.

14. The semiconductor structure of claim 12 wherein at least one layer selected from the group consisting of the first stressed silicon nitride layer and the second stressed silicon nitride layer is patterned according to a well mask.

15. The semiconductor structure of claim 12 wherein the first stressed silicon nitride layer extends from a first isolation dielectric across the drain region, gate and source region to a second isolation dielectric.

16. The semiconductor structure of claim 12 wherein the first stressed silicon nitride layer is a chemical etch stop layer.

17. The semiconductor structure of claim 12 wherein the first stressed silicon nitride layer fills the first recess and the second recess.

18. The semiconductor structure of claim 12 wherein the transistor is a PMOS transistor and the first stressed silicon nitride layer is a compressive silicon nitride layer.

19. The semiconductor structure of claim 12 wherein the transistor is an NMOS transistor and the first stressed silicon nitride layer is a tensile silicon nitride layer.