Technique for evaluating a fabrication of a die and wafer

• US 7,423,288 B2
• Filed: 04/20/2007
• Issued: 09/09/2008
• Est. Priority Date: 08/25/2003
• Status: Active Grant

• Current Assignee: Tau-Metrix, Inc.
• Original Assignee: Tau-Metrix, Inc.
• Inventors: Pakdaman, Nader, Aghababazadeh, Majid, Steinbrueck, Gary L., Vickers, James S., Estabil, Jose J.
• Primary Examiner(s): Tran; Long K
• Application Number:
  US11/738,219
• Publication Number:
  US 20070187679A1
• Time in Patent Office: 508 Days
• Field of Search: 257/48, 257/E21.521, 257/14, 257/11, 257/18, 257/E21.525, 257/620, 257/E21.524, 438/11, 438/14, 438/18, 438/15
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter of the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Claims

1. An arrangement of test structures provided on at least a partially completed wafer, the arrangement comprising:

a plurality of test structures positioned on at least one die, and wherein individual test structures in the plurality of test structures are identifiable in formation or location as being part of any one or more of a plurality of classes, wherein each of the plurality of test structures is capable of being activated to cause an electrical activity that is detectable;

wherein each test structure is configured so that (i) the electrical activity that is caused by activation of that test structure identifies a value that indicates an attribute or result of one or more steps that comprise the design or fabrication, and (ii) the electrical activity that is caused by activation of that test structure is not indicative of another step in the design or fabrication;

wherein the wafer includes a class of the test structures for each step in the set of designated steps;

wherein the identified value from each class of test structures can be used, either individually or in combination with the value of another class of test structures, to determine information about the design or fabrication of the wafer.

2. The arrangement of claim 1, wherein the plurality of test structures are activated and triggered concurrently.

3. The arrangement of claim 2, wherein the electrical activity that is detectable from at least some of the plurality of test structures identify either (i) those test structures from other test structures on the wafer, or (ii) individual locations of those test structures on the wafer.

4. The arrangement of claim 3, wherein the electrical activity that is detectable from at least some of the plurality of test structures are detectable using a common detection apparatus that scans at least some of the wafer without making contact.

5. The arrangement of claim 1, wherein one or more of the plurality of test structures are each configured so that the electrical activity that is detectable from those one or more test structures is indicative of a particular physical or electrical characteristic that is present within an active region of the wafer, wherein the physical or electrical characteristic is associated with the design or fabrication step.

6. The arrangement of claim 1, wherein one or more of the plurality of test structures are tiggerable by a common energy beam.

7. The arrangement of claim 6, wherein the electrical activity that is detectable from one or more of the plurality of test structures includes photons produced from a switch element that comprises at least a portion of the one or more test structures.

8. The arrangement of claim 1, wherein the electrical activity that is detectable from one or more of the plurality of test structures includes at least one of an electrostatic, electromagnetic, inductive or capacitive signal that is created by an output of each of the one or more test structures in response to being activated or triggered.

9. The arrangement of claim 1, wherein the electrical activity that is detected some of the plurality of test structure includes a radio-frequency.

10. The arrangement of claim 1, wherein one or more of the plurality of test structures includes a plurality of interconnected inverters.

11. The arrangement of claim 10, wherein one or more of the plurality of test structures includes one or more CMOS inverters.

12. The arrangement of claim 1, wherein one or more of the plurality of test structures are configured so that the electrical activity that is caused by activation of those one or more test structures reduces a sensitivity to a variation amongst a relationship of transistor gate lengths to transistor gate widths.

13. The arrangement of claim 1, wherein one or more of the plurality of test structures each are configured so that the electrical activity that is caused by activation of those one or more test structures exaggerates the influence of transistor gate widths to transistor gate lengths.

14. The arrangement of claim 1, wherein one or more of the plurality of test structures include one or more transistors and a device interconnect that are combined and configured so that the electrical activity that is caused by activation of those one or more test structures combine to exaggerate an influence of interconnect resistance.

15. The arrangement of claim 1, wherein one or more of the plurality of test structures include one or more transistors and device interconnect that are combined and configured so that the electrical activity that is caused by activation of those one or more test structures exaggerate an influence of interconnect capacitance.

16. The mechanism of claim 1, wherein one or more of the plurality test structures includes a combination of device and interconnect elements that are configured so that the electrical activity that is caused by activation of those device and interconnect elements exaggerate an influence of gate capacitance.

17. The mechanism of claim 16, wherein one or more of the plurality of test structures are configured so that the electrical activity that is caused by activation of those one or more test structures exaggerate an influence of a gate film stack on gate.

18. The mechanism of claim 1, wherein one or more of the plurality of test structures include a plurality of transistors and an interconnect device that are configured, so that the electrical activity that is caused by activation of those one or more transistors and the interconnect device combine to exaggerate an influence of contact resistance.

19. The mechanism of claim 1, wherein one or more of the plurality of test structures are configured so that the electrical activity that is caused by activation of those one or more test structures exaggerate an influence of contact resistance.

20. An arrangement of test structures provided on at least a partially completed wafer, the arrangement comprising:

a plurality of test structures positioned on at least one die, and wherein individual test structures in the plurality of test structures are identifiable in formation or location as being part of any one or more of a plurality of classes, wherein each of the plurality of test structures is capable of being activated to cause an electrical activity that is detectable;

wherein the test structures that comprise a given class of test structures are designed and structured, and/or located, so that the electrical activity that is caused by activation of the test structures of the class identify one or more values that are indicative of one or more of a particular physical or electrical characteristic of either the wafer, or a portion thereof or a device on the wafer, when the wafer is in at least the partially completed state.

21. The arrangement of claim 20, wherein the test structures that comprise the given class of test structures are located in an active region of a die on the wafer.

22. The arrangement of claim 20, wherein the test structures that comprise the given class of test structures are designed and structured, and/or located, so as to exaggerate a particular physical or electrical characteristic when the wafer is in a particular state of fabrication.

23. The arrangement of claim 20, wherein the plurality of test structures include a first class of test structures that are sensitive to a condition or criteria or the wafer at a given instance, and a second class of test structures that are insensitive to that condition or criteria of the wafer at the given instance.

24. The arrangement of claim 20, wherein one or more of the plurality of test structures that comprise the given class include (i) a first element that is sensitive to a particular condition that is present on one or more of the wafer or portion thereof, or on a device on the wafer, and (ii) a second element that is insensitive to the particular condition, and wherein the first element and the second element are coupled to be activated from a common source of activation at a given location of the wafer.

25. The arrangement of claim 24, wherein the first element and the second element are coupled to be electrically powered and activated in parallel with respect to the common source.

26. The arrangement of claim 25, the one or more of the plurality of test structures that comprise the given class also each include the common source of activation.

27. The arrangement of claim 24, wherein the first element and the second element are configured to provide or behave as a ring oscillator.

28. The arrangement of claim 20, wherein one or more of the plurality of test structures that comprise the given class are designed and structured to include physical and/or electrical device and circuit elements that are used for functioning or completed devices or cells in an active region of the wafer in a completed state, and wherein the one or more of the plurality of test structures are formed on the wafer when the wafer is in a partially completed state.

29. The arrangement of claim 28, wherein the one or more of the plurality of test structures that comprise the given class include (i) a first element that is designed and structured to be sensitive to a particular condition that is present on one or more of the wafer or portion thereof or on a device on the wafer, and (ii) a second element that is designed and structured to be insensitive to the particular condition, and wherein the first element and the second element are coupled to be activated from a common source of activation at a given location of the wafer.

30. The arrangement of claim 20, wherein individual test structures that comprise the given class of test structures include one or more test structures that comprise a first element and a second element, the first and second elements being designed so that the first element is sensitive to a first condition that is present on the wafer in the partially completed state, and the second element is insensitive to the first condition, and wherein the first element and the second element are capable of being activated from a common source and each include a respective first and second output that is separately measured, so that, when compared, a differential measurement made between the output of the first element and the output the second element is indicative of a systematic or randomness of variations of electrical activity present on that wafer.

31. The arrangement of claim 20, wherein the test structures that comprise the given class of test structures are formed, located, or designed so as to individually, or collectively with one or more other test structures in the plurality of test structures, exaggerate the particular physical or electrical characteristic resulting from performing one or more processes to design or fabricate the wafer.

32. The arrangement of claim 31, wherein the test structures that comprise the given class of test structures include single or multiple ring oscillators.

33. The arrangement of claim 31, wherein one or more of the plurality of test structures that comprise the given class include (i) a first element that is sensitive to the particular physical or electrical characteristic, and (ii) a second element that is insensitive to the particular physical or electrical characteristic, and wherein the first element and the second element are coupled to be activated from a common source of activation at a given location of the wafer.

34. The arrangement of claim 33, wherein the first element and the second element are activatable from a common source and each include a respective first and second output that is separately measured, so that the particular result is provided by a differential measurement made by comparing the output of the first element and the output of the second element, the particular result being indicative of a systematic or randomness of variations of electrical activity present on that wafer.

35. The arrangement of claim 33, wherein the particular result corresponds to interconnect resistivity or capacitance, or a combination thereof, at one or more locations on the wafer or on a device of the wafer.

36. The arrangement of claim 33, wherein the one or more processes to design or fabricate the wafer include one or more patterning processes or sub-processes.

37. The arrangement of claim 33, wherein the one or more patterning processes or sub-processes include a pattern-mask process, a photoresist process, a dose-exposure process, or an etch process.

38. The arrangement of claim 33, wherein the one or more processes to design or fabricate the wafer include one or more of a deposition process, a diffusion process, a polishing process, an aneal process, or a planarization or polishing process.

39. The arrangement of claim 31, wherein the particular physical or electrical characteristic corresponds to a device semiconductor junction physical and/or electrical characteristic at one or more locations on the wafer, or portion thereof.

40. The arrangement of claim 31, wherein the particular physical or electrical characteristic corresponds to a device gate physical and/or electrical characteristic at one or more locations on the wafer, or portion thereof.