Post passivation interconnection process and structures

• US 7,423,346 B2
• Filed: 09/09/2004
• Issued: 09/09/2008
• Est. Priority Date: 09/09/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming
• Primary Examiner(s): Pham; Thanhha
• Application Number:
  US10/937,543
• Publication Number:
  US 20060049524A1
• Time in Patent Office: 1,461 Days
• Field of Search: 257/531, 257/533, 257/758, 257/762, 257/759, 257763-765, 257/773, 257/E23.141
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/04953 TaN
• CPC Class Codes: H01L 2924/05042 Si3N4
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19015 including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. A circuit component with a post-passivation interconnection structure, comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure and over said dielectric layer, wherein said passivation layer comprises a topmost nitride of said circuit component and a topmost oxide of said circuit component, and wherein a first opening in said passivation layer is over a first contact point of said first metallization structure and exposes said first contact point, and a second opening in said passivation layer is over a second contact point of said first metallization structure and exposes said second contact point, wherein there is an insulating layer between said first contact point and said second contact point, and wherein said first contact point is directly over said transistor;

a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers;

a second metallization structure on said first polymer layer and over said first and second contact points, wherein a first product of resistance of a first section of a metal trace of said second metallization structure times capacitance of said first section is smaller than a second product of resistance of a second section of a metal trace of said first metallization structure times capacitance of said second section by at least 10 times, said first section having a same length as said second section, wherein said second metallization structure connects said first and second contact points, and wherein said second metallization structure comprises a titanium-containing layer, a gold seed layer having a thickness between 300 and 3,000 angstroms on said titanium-containing layer, and a gold bulk layer having a thickness between 1 and 20 micrometers on said gold seed layer, wherein an undercut with an edge of said titanium-containing layer recessed from an edge of said gold bulk layer is between 0.1 and 1 micrometer; and

a second polymer layer on said second metallization structure.

2. The circuit component of claim 1, wherein said first polymer layer comprises polyimide.

3. The circuit component of claim 1, wherein said first polymer layer comprises benzocyclobutene (BCB).

4. The circuit component of claim 1, wherein said first polymer layer comprises parylene.

5. The circuit component of claim 1, wherein said first polymer layer comprises an epoxy-based material.

6. The circuit component of claim 1, wherein said titanium-containing layer further comprises tungsten.

7. The circuit component of claim 1, wherein said titanium-containing layer further comprises nitride.

8. The circuit component of claim 1, wherein a third opening in said first polymer layer exposes said first contact point, and a fourth opening in said first polymer layer exposes said second contact point.

9. The circuit component of claim 1, wherein said dielectric layer comprises silicon oxide.

10. The circuit component of claim 1, wherein said dielectric layer comprises fluorosilicate glass.

11. The circuit component of claim 1, wherein said dielectric layer comprises TEOS oxide.

12. The circuit component of claim 1, wherein said dielectric layer comprises spin-on glass.

13. The circuit component of claim 1, wherein said first metallization structure comprises aluminum.

14. The circuit component of claim 1, wherein said first metallization structure comprises damascene copper.

15. The circuit component of claim 1, wherein said first product is smaller than said second product by at least 100 times.

16. The circuit component of claim 1, wherein said first product is smaller than said second product by at least 1000 times.

17. The circuit component of claim 1, wherein said first product is smaller than said second product by at least 10,000 times.