Method of performing parallel test on semiconductor devices by dividing voltage supply unit

• US 7,423,443 B2
• Filed: 01/10/2006
• Issued: 09/09/2008
• Est. Priority Date: 01/11/2005
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sang-Hoon, Ahn, Jung-Bae, Ji, Joon-Su
• Primary Examiner(s): Nguyen; Vinh P
• Application Number:
  US11/330,013
• Publication Number:
  US 20060152242A1
• Time in Patent Office: 973 Days
• Field of Search: 324754-769, 714/724, 702115-117
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

Provided is a method of performing a parallel test on semiconductor devices, the method including coupling a power signal line to a set of at least two semiconductor devices through a switching device, performing at least one part of a parallel test on the set of semiconductor devices, and disconnecting a semiconductor device from the set in response to determining that the semiconductor device is defective as a result of the at least one part of the parallel test.

Claims

1. A method of performing a parallel test, the method comprising:

coupling a power signal line to a set of at least two semiconductor devices through a switching device, each semiconductor device of the set coupled to the switching device through a common node;

performing at least one part of a parallel test on the set of semiconductor devices; and

disconnecting a semiconductor device from the set in response to determining that the semiconductor device is defective as a result of the at least one part of the parallel test.

2. The method of claim 1, further comprising disconnecting the set of semiconductor devices from the power signal line in response to determining that at least one semiconductor device of the set is defective and determining that less than all of the semiconductor devices of the set are defective as a result of the at least one part of the parallel test.

3. The method of claim 1, wherein the semiconductor devices are semiconductor memory devices.

4. The method of claim 1, wherein disconnecting the semiconductor device from the set further comprises using a switching device to disconnecting the semiconductor device from the set, the switching device including a circuit module including a relay.

5. The method of claim 1, disconnecting the semiconductor device from the set further comprises disconnecting the semiconductor device from the set in response to a signal on a signal line of a performance board.

6. The method of claim 5, wherein the signal line is one of an input/output signal line and a driver signal line, the driver signal line for driving a signal on at least one of the semiconductor devices of the set and the input/output signal line for inputting and outputting a signal from at least one of the semiconductor devices of the set.

7. The method of claim 5, further comprising using the signal line to electrically test the semiconductor devices.

8. The method of claim 5, further comprising generating the signal in response to a test program used in the part of the parallel test.

9. The method of claim 8, generating the signal further comprising controlling a voltage on the signal line.

10. The method of claim 1, wherein disconnecting the semiconductor device from the set is performed after a test of the parallel test selected from the group consisting of an open/short test and a leakage test.

11. The method of claim 1, wherein performing the at least one part of the parallel test further comprises:

connecting an automatic test robot including an interface board to a performance board; and

starting the at least one part of the parallel test using the automatic test robot.

12. The method of claim 11, wherein the interface board is one selected from the group consisting of a probe card and a device under test board.

13. The method of claim 12, wherein the automatic test robot is one selected from the group consisting of a prober system and a handler.

14. The method of claim 1, further comprising coupling each semiconductor device to the common node through an associated path external to the set of semiconductor devices and different from the path associated with another semiconductor device of the set.

15. The method of claim 1, the switching device referred to as a first switching device, the method further comprising coupling each semiconductor device to the common node through an associated second switching device different from other second switching devices for coupling other semiconductor devices of the set to the common node.