Fully integrated tuner architecture

• US 7,423,699 B2
• Filed: 03/31/2006
• Issued: 09/09/2008
• Est. Priority Date: 11/12/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Vorenkamp, Pieter, Duncan, Ralph, Carr, Frank, Kwan, Tom W., Khorramabadi, Haideh, Ward, Christopher M., Chang, James Y. C., Bult, Klaas
• Primary Examiner(s): HSIA, SHERRIE Y
• Application Number:
  US11/393,899
• Publication Number:
  US 20070077908A1
• Time in Patent Office: 893 Days
• Field of Search: 348/731, 348725-727, 455/266, 455/296, 455313-315, 455/337, 455/302, 455338-340, 455/179.1, 455/207, 455/196.1, 455/305, 455/202, 455/205, 455/188.1, 455/208, 455/189.1, 455/209, 455/190.1, 455/303, 455/191.1, 725/151
• US Class Current: 348/726
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 27/42 Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 3/18 by means of synchronous gating arrangements
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/3211 : in differential amplifiers
• CPC Class Codes: H03F 2200/111 : the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 : Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/447 : the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/63 : the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 2203/45264 : the dif amp comprising frequency or phase stabilisation means
• CPC Class Codes: H03F 2203/45286 : the temperature dependence of a differential amplifier being controlled
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0023 : in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03G 3/3052 : in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03H 11/04 : Frequency selective two-port networks
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03H 11/53 : simulating resistances; simulating resistance multipliers
• CPC Class Codes: H03H 11/54 : Modifications of networks to reduce influence of variations of temperature
• CPC Class Codes: H03H 19/004 : Switched capacitor networks
• CPC Class Codes: H03H 7/25 : comprising an element controlled by an electric or magnetic variable H03H7/27 takes precedence
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 2207/06 : Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/183 : a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Claims

1. An integrated receiver comprising:

a substrate providing a physical medium upon which a receiver circuit is disposed;

a mixer having its circuit elements disposed upon the substrate for converting a received signal to a first IF;

a first filter bank having its circuit elements disposed upon the substrate for removing an image distortion from the first IF and removing unwanted channels; and

an I/Q mixer disposed upon the substrate for converting the first IF to a second IF and rejecting a first IF image distortion.

2. The integrated receiver of claim 1, further comprising:

a second filter bank having its circuit elements disposed upon the substrate for removing an image distortion and unwanted channels from the second IF;

whereby frequency conversion, channel selectivity and all image rejection are performed on an integrated circuit.

3. The integrated receiver of claim 1, wherein the mixer, the first filter, and the I/Q mixer are configured for differential signal processing.

4. The integrated receiver of claim 1, further comprising:

a first LO generator disposed on the integrated receiver substrate, configured to provide a first local oscillator signal to the mixer; and

a second LO generator disposed on the integrated receiver substrate, configured to provide a second local oscillator signal.

5. The integrated receiver of claim 4, wherein the first LO generator comprises a wide band phase lock loop (PLL) coupled to a reference signal generator.

6. The integrated receiver of claim 4, wherein the second LO generator comprises:

a reference signal generator;

a narrow band PLL coupled to the reference signal generator; and

a poly phase circuit coupled to the narrow band PLL producing image and quadrature second LO signals from the narrow band PLL signal.

7. The integrated receive of claim 1, wherein the filter bank comprises:

a multi-track spiral inductor; and

a compensation circuit that compensates for variations in the multi-track spiral inductor Q over temperature.

8. The integrated receiver of claim 7, wherein the compensation circuit includes:

a first field effect transistor in series with the multi-track spiral inductor;

a dummy multi-track spiral inductor; and

a second field effect transistor in series with the dummy multi-track spiral inductor acting as a control element to maintain a constant voltage across the dummy multi-track spiral inductor, the gate of the second field effect transistor coupled to the gate of the first field effect transistor.

9. The integrated circuit of claim 8, wherein the dummy multi-track spiral inductor has a temperature characteristic that tracks that of the multi-track spiral inductor.

10. The integrated receiver of claim 7, wherein the multi-track spiral inductor includes a series resistance that varies proportionally with temperature, wherein said compensation circuit includes:

an amplifier having a positive input terminal, a negative input terminal, and an output terminal;

first and second variable resistors each having a first terminal, a second terminal, and a control terminal, wherein the respective control terminals are coupled to the output terminal of the amplifier;

a resistor coupled in series between the negative input terminal of the amplifier and the first terminal of the second variable resistor; and

a dummy filter element coupled in series between the positive input terminal of the amplifier and the second terminal of the second variable resistor.

11. A method for processing a RF signal having a plurality of channels, comprising:

(1) mixing the RF signal with a first differential local oscillator signal to produce a first differential IF signal;

(2) filtering the first differential IF signal using a differential filter having a passband that is higher in frequency than the RF signal to produce a second differential IF signal;

(3) adjusting the first local oscillator signal so that a selected channel in the plurality of channels is shifted into a passband of the differential filter;

(4) generating a second differential local oscillator signal having I and Q components; and

(5) mixing the second differential IF signal with a second differential local oscillator signal to produce a second differential IF signal,

wherein steps (1)-(5) are performed on a common substrate.

12. The method of claim 11, wherein the plurality of channels are television channels.

13. The method of claim 11, further comprising the step of:

(6) filtering the second differential IF signal on the common substrate to remove at least one unwanted channel from the second differential IF signal.

14. The method of claim 11, further comprising the step of:

(6) performing automatic gain control on the second IF signal on the common substrate.

15. The method of claim 14, wherein step (6) includes the step of removing at least one unwanted image from the second differential IF signal.

16. The method of claim 11, wherein the differential filter includes a multi-track spiral inductor, the method further comprising the step of:

compensating for variations in the multi-track spiral inductor Q over temperature.