Circuit-pattern inspecting apparatus and method

• US 7,423,746 B2
• Filed: 01/29/2007
• Issued: 09/09/2008
• Est. Priority Date: 02/28/2006
• Status: Expired due to Fees

• Current Assignee: Hitachi High Technologies America (Hitachi, Ltd.)
• Original Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Inventors: Ito, Hirokazu, Takeda, Masayoshi
• Primary Examiner(s): Lauchman; L. G.
• Assistant Examiner(s): ALLI, IYABO
• Application Number:
  US11/698,985
• Publication Number:
  US 20070201018A1
• Time in Patent Office: 589 Days
• Field of Search: 3562372-2376, 250306-310
• US Class Current: 356/237.4
• CPC Class Codes: G01N 2021/9513 Liquid crystal panels
• CPC Class Codes: G01N 2021/95676 Masks, reticles, shadow masks
• CPC Class Codes: G01N 21/95607 using a comparative method

Abstract

A circuit pattern inspection apparatus and inspection method facilitate the creation of a recipe and the confirmation of a defect. The apparatus and method employ a dialogue-based operation for the creation of a recipe and the confirmation of a defect. Input items (such as contrast, calibration, etc.) for the recipe creation and their purposes are clarified. Input items (such as clustering, filtering, etc.) for the defect confirmation and their purposes are also clarified. The results obtained on the basis of these inputs are registered in the recipe.

Claims

1. A circuit pattern inspection apparatus comprising:

an irradiation means for irradiating the surface of a substrate on which a wafer circuit pattern is formed with either light, laser light, or a charged-particle beam;

a detection means for detecting a signal produced by the substrate upon irradiation;

an inspection image acquisition means for acquiring images of the wafer circuit pattern as inspection images by converting the signal detected by the detection means into images;

a defect determination means for comparing the inspection images obtained by the inspection image acquisition means with a reference image different from the inspection images that are acquired from an identical circuit pattern so as to determine a defect portion produced on the circuit pattern from which the inspection images have been acquired;

an analysis result display means for generating a defect confirmation screen on which the inspection images acquired by the inspection image acquisition means, an analysis image based on the inspection images, and another analysis image based on the result of defect determination made by the defect determination means are arranged;

an input means for entering information on a defect confirmation screen generated by the analysis result display means in a dialog mode; and

an image linkage means for changing, when an operation input has been made using the input means on either the analysis image based on the inspection images disposed or on the analysis image based on the result of determination that are arranged on the defect confirmation screen, the display contents of one analysis image are changed in a corresponding manner in operative linkage with the operation input made on the other analysis image via the input means.

2. The circuit pattern inspection apparatus according to claim 1, wherein the analysis result display means generates at least one analysis image based on the inspection image disposed on the defect confirmation screen using the input means, or based on the result of defect determination made by the defect determination means.

3. The circuit pattern inspection apparatus according to claim 1, wherein the input means comprises means for selecting an irradiation condition for the irradiation means via the defect confirmation screen.

4. The circuit pattern inspection apparatus according to claim 2, wherein the input means also functions as a recipe setting means for setting an irradiation condition for the irradiation means as recipe data, wherein the irradiation condition is selected on the defect confirmation screen.

5. A circuit pattern inspection method comprising the steps of:

irradiating the surface of a substrate on which a wafer circuit pattern is formed with light, laser light, or a charged-particle beam;

detecting a signal produced by the substrate upon irradiation;

imaging the thus detected signal and acquiring images of the wafer circuit pattern as inspection image images;

comparing the inspection images with a reference image that is separated from the inspection images and that is acquired from an identical circuit pattern; and

determining a defect portion produced on the circuit pattern from which the inspection images have been acquired, based on the result of comparison,

the method further comprising;

an analysis result display step of generating a defect confirmation screen on which the inspection images, an analysis image based on the inspection images and an analysis image based on the result of defect determination are arranged;

an input step of entering information on the defect confirmation screen generated in the analysis result display step in a dialog mode; and

an image linkage step of changing, when an operation input has been made using the input means on either the analysis image based on the inspection images disposed or on the analysis image based on the result of determination that are arranged on the defect confirmation screen, the display contents of one analysis image are changed in a corresponding manner in operative linkage with the operation input made on the other analysis image via the input means.