Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices

• US 7,424,552 B2
• Filed: 07/11/2003
• Issued: 09/09/2008
• Est. Priority Date: 12/17/1997
• Status: Expired due to Fees

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Computers, Inc.
• Inventors: Burton, Lee A.
• Primary Examiner(s): Sorrell; Eron J
• Application Number:
  US10/618,041
• Publication Number:
  US 20040019703A1
• Time in Patent Office: 1,887 Days
• Field of Search: None
• US Class Current: 709/250
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2213/3808 Network interface controller

Abstract

An enhanced switch/network adapter port (“SNAP™”) including collocated shared memory resources (“SNAPM™”) in a dual in-line memory module (“DIMM”) or any other memory module format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain. This provides the highest performance link to the other network devices such as MAP® elements, common memory boards and the like.

Claims

1. A computer system comprising:

at least one dense logic device;

a controller coupling said at least one dense logic device to a control block and a memory bus;

one or more memory module slots coupled to said memory bus;

an adapter port associated with a subset of said one or more memory module slots, said adapter port including associated memory resources, wherein said control block provides control information to said adapter port and wherein said adapter port shares access control to said memory resources with said controller such that when said controller is in control of said memory resources said adapter port is barred from accessing said memory resources and when said adapter port is in control of said memory resources said controller is disconnected from said memory resources and wherein said controller is disconnected from said memory resources said adapter port monitors said control block for control information; and

at least one direct execution logic element coupled to said adapter port, said memory resources being substantially equally accessible by said at least one dense logic device and said at least one direct execution logic element.

2. The computer system of claim 1 wherein said controller comprises an interleaved memory controller that is bi-directionally coupled to the at adaptor port and said one or more memory module slots, and wherein said controller includes a plurality of control registers configured to control shared use of said memory resources.

3. The computer system of claim 1 wherein said plurality of memory module slots comprise DIMM memory module slots.

4. The computer system of claim 3 wherein said adapter port comprises a DIMM physical format for retention within one of said DIMM memory module slots.

5. The computer system of claim 1 wherein said plurality of memory module slots comprise in-line memory module serial interface slots.

6. The computer system of claim 5 wherein said adapter port comprises a in-line memory module serial interface physical format for retention within one of said in-line memory module serial interface slots.

7. The computer system of claim 1 wherein said control block provides control information to said direct execution logic element.

8. The computer system of claim 1 wherein said control block comprises a peripheral bus control block.

9. The computer system of claim 8 wherein said peripheral bus control block provides control information to said adapter port.

10. The computer system of claim 8 wherein said peripheral control block provides control information to said direct execution logic element.

11. The computer system of claim 1 wherein said control block comprises a graphics control block.

12. The computer system of claim 11 wherein said graphics control block provides control information to said adapter port.

13. The computer system of claim 11 wherein said graphics control block provides control information to said direct execution logic element.

14. The computer system of claim 1 wherein said control block comprises a systems maintenance control block.

15. The computer system of claim 14 wherein said systems maintenance control block provides control information to said adapter port.

16. The computer system of claim 14 wherein said systems maintenance control block provides control information to said direct execution logic element.

17. The computer system of claim 1 wherein said direct execution logic element comprises a reconfigurable processor element.

18. The computer system of claim 1 wherein said direct execution logic element is operative to alter data received from said controller on said memory bus.

19. The computer system of claim 1 wherein said direct execution logic element is operative to alter data received from an external source prior to placing altered data on said memory bus.

20. The computer system of claim 1 wherein said direct execution logic element comprises:

a control block coupled to said adapter port.

21. The computer system of claim 20 wherein said direct execution logic element further comprises:

at least one field programmable gate array configurable to perform an identified algorithm on and operand provided thereto by said adapter port.

22. The computer system of claim 21 further comprising:

a dual-ported memory block coupling a control block coupled to said adapter port to said at least one field programmable gate array.

23. The computer system of claim 20 wherein said direct execution logic element further comprises:

a read only memory associated with said control block for providing configuration information thereto.

24. The computer system of claim 1 wherein said direct execution logic element comprises:

a chain port for coupling said direct execution logic element to another direct execution logic element.

25. A computer system comprising:

at least one dense logic device;

an interleaved controller coupling said at least one dense logic device to a control block and a memory bus;

a plurality of memory slots coupled to said memory bus;

an adapter port associated with at least two of said plurality of memory slots, each of said adapter port including associated memory resources, wherein said control block provides control information to said adapter port and wherein said adapter port shares access control to said memory resources with said controller such that when said controller is in control of said memory resources said adapter port is barred from accessing said memory resources and when said adapter port is in control of said memory resources said controller is disconnected from said memory resources and wherein said controller is disconnected from said memory resources said adapter port monitors said control block for control information; and

a direct execution logic element coupled to at least one of said adapter ports, said memory resources being substantially equally accessible by said at least one dense logic device and said direct execution logic element.

26. The computer system of claim 25 wherein said plurality of memory slots comprise DIMM memory module slots.

27. The computer system of claim 26 wherein said adapter port comprises a DIMM physical format for retention within one of said DIMM memory module slots.

28. The computer system of claim 25 wherein said plurality of memory slots comprise in-line memory module serial interface slots.

29. The computer system of claim 28 wherein said adapter port comprises a in-line memory module serial interface physical format for retention within one of said in-line memory module serial interface slots.

30. The computer system of claim 25 wherein said control block provides control information to said direct execution logic element.

31. The computer system of claim 25 wherein said control block comprises a peripherai bus controi block.

32. The computer system of claim 31 wherein said peripheral bus control block provides control information to said adapter port.

33. The computer system of claim 31 wherein said peripheral control block provides control information to said direct execution logic element.

34. The computer system of claim 25 wherein said control block comprises a graphics control block.

35. The computer system of claim 34 wherein said graphics control block provides control information to said adapter port.

36. The computer system of claim 34 wherein said graphics control block provides control information to said direct execution logic element.

37. The computer system of claim 25 wherein said control block comprises a systems maintenance control block.

38. The computer system of claim 37 wherein said systems maintenance control block provides control information to said adapter port.

39. The computer system of claim 37 wherein said systems maintenance control block provides control information to said direct execution logic element.

40. The computer system of claim 25 wherein said control block comprises a PCI-X control block.

41. The computer system of claim 40 wherein said PCI-X control block provides control information to said adapter port.

42. The computer system of claim 40 wherein said PCI-X control block provides control information to said direct execution logic element.

43. The computer system of claim 25 wherein said control block comprises a PCI Express control block.

44. The computer system of claim 43 wherein said PCI Express control block provides control information to said adapter port.

45. The computer system of claim 43 wherein said PCI Express control block provides control information to said direct execution logic element.

46. The computer system of claim 25 wherein said direct execution logic element comprises a reconfigurable processor element.

47. The computer system of claim 25 wherein said direct execution logic element is operative to alter data received from said controller on said memory bus.

48. The computer system of claim 25 wherein said direct execution logic element is operative to alter data received from an external source prior to placing altered data on said memory bus.

49. The computer system of claim 25 wherein said direct execution logic element comprises:

a control block coupled to said adapter port.

50. The computer system of claim 49 wherein said direct execution logic element further comprises:

at least one field programmable gate array configurable to perform an identified algorithm on and operand provided thereto by said adapter port.

51. The computer system of claim 50 further comprising:

a dual-ported memory block coupling a control block coupled to said adapter port to said at least one field programmable gate array.

52. The computer system of claim 49 wherein said direct execution logic element further comprises:

a read only memory associated with said control block for providing configuration information thereto.

53. The computer system of claim 25 wherein said direct execution logic element comprises:

a chain port for coupling said processor element to another direct execution logic element.

54. A computer system including an adapter port for electrical coupling between a memory bus of said computer system and a network interface, said computer system comprising at least one dense logic device coupled to said memory bus and said memory bus comprising at least one memory module slot, said adapter port comprising:

a memory resource associated with said adapter port wherein said adapter port is configured for physical retention within said at least one memory module slot; and

a control block for selectively enabling access by said at least one dense logic device to said memory resource, wherein said control block provides control information to said adapter port and wherein said adapter port shares access control to said memory resource with said controller such that when said controller is in control of said memory resource said adapter port is barred from accessing said memory resource and when said adapter port is in control of said memory resource said controller is disconnected from said memory resource and wherein said controller is disconnected from said memory resource said adapter port monitors said control block for control information.

55. The computer system of claim 54 wherein said control block is further operational to selectively preclude access by said at least one dense logic device to said memory resource.

56. The computer system of claim 54 further comprising:

at least one direct execution logic element coupled to said network interface.

57. The computer system of claim 56 wherein said control block is further operational to alternatively enable substantially equal access to said memory resource by said at least one dense logic device and said at least one direct execution logic element.

58. The computer system of claim 54 wherein said at least one memory module slot comprises a DIMM slot.

59. The computer system of claim 54 wherein said at least one memory module slot comprises a in-line memory module serial interface slot.

60. The computer system of claim 54 further comprising:

an additional adapter port;

an additional memory resource associated with said additional adapter port, said control block further operative to selectively enable access by said at least one dense logic device to said additional memory resource.

61. The computer system of claim 60 wherein said control block is further operational to selectively preclude access by said at least one dense logic device to said memory resource and said additional memory resource.

62. The computer system of claim 61 further comprising at least one direct execution logic element coupled to said network interface.

63. The computer system of claim 62 wherein said control block is further operational to alternatively enable access to said memory resource and said additional memory resource by said at least one dense logic device and said at least one direct execution logic element.

64. The computer system of claim 60 wherein said memory bus further comprises first and second memory module slots for physical retention of said at least one adapter port and said additional adapter port respectively.

65. The computer system of claim 64 wherein said first and second memory module slots comprise DIMM slots.

66. The computer system of claim 64 wherein said first and second memory module slots comprise in-line memory module serial interface slots.

67. The computer system of claim 60 wherein said control block is located on a module comprising said adapter port.

68. The computer system of claim 54 wherein said computer system further comprises:

a memory and I/O controller interposed between said at least one dense logic device and said memory bus.

69. The computer system of claim 68 wherein said memory and I/O controller comprises an interleaved memory controller.

70. The computer system of claim 54 wherein said adapter port comprises a number of switches interposed between said memory bus and said memory resource controllable by said control block.

71. The computer system of claim 70 wherein said switches comprise field effect transistors.

72. The computer system of claim 70 wherein said switches have a first condition thereof for coupling said dense logic device to said memory resource and a second condition thereof for coupling said network interface to said memory resource.

73. The computer system of claim 54 wherein said memory bus comprises address/control and data portions thereof.

74. The computer system of claim 54 wherein said memory bus provides address/control and data inputs to said control block to at least partially control its functionality.

75. The computer system of claim 54 wherein said control block further comprises a DMA controller for providing direct memory access operations to said memory resource.

76. The computer system of claim 75 wherein said DMA controller is fully parameterized.

77. The computer system of claim 75 wherein said DMA controller enables scatter/gather functions to be implemented.

78. The computer system of claim 75 wherein said DMA controller enables irregular data access pattern functions to be implemented.

79. The computer system of claim 75 wherein said DMA controller enables data packing functions to be implemented.

80. The computer system of claim 54 wherein said memory resource may be isolated from said memory bus in response to said control block to enable access thereto by a device coupled to said network interface.

81. The computer system of claim 54 wherein said memory resource comprises random access memory.

82. The computer system of claim 81 wherein said random access memory comprises DRAM.