Memory controller for processor having multiple multithreaded programmable units

• US 7,424,579 B2
• Filed: 09/21/2005
• Issued: 09/09/2008
• Est. Priority Date: 08/31/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wheeler, William R., Wolrich, Gilbert, Adiletta, Matthew J., Burres, Bradley
• Primary Examiner(s): Sparks; Doanld
• Assistant Examiner(s): DILLER, JESSE DAVID
• Application Number:
  US11/232,566
• Publication Number:
  US 20060069882A1
• Time in Patent Office: 1,084 Days
• Field of Search: 711/151
• US Class Current: 711/151
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Claims

1. A processor chip, comprising:

multiple programmable units integrated in the processor chip, wherein at least some of the multiple programmable units integrated in the processor chip comprise multi-threaded programmable units having multiple program counters corresponding to multiple threads of program execution;

a random access memory controller integrated in the processor chip to couple to an off-chip random access memory, the random access memory controller coupled to the multiple programmable units integrated in the processor chip, the random access memory controller comprising logic to enqueue entries for memory reference requests received from the multiple programmable units into one of multiple queues and select from the enqueued entries to initiate a memory access operation of the off-chip random access memory,

wherein the random access memory controller logic to select from the enqueued entries comprises logic to select from the enqueued entries in an order that differs from the order in which the memory reference requests are received from the multiple programmable units.

2. The processor chip of claim 1,

wherein the multiple queues comprise at least one queue to store entries for memory reference requests for a particular one of the multiple programmable units;

and

wherein the random access memory controller logic comprises logic to enqueue entries for at least some of the memory reference requests received from the particular one of the multiple programmable units in the at least one queue to store entries for memory reference requests for the particular one of the multiple programmable units.

3. The processor chip of claim 1,

wherein the multiple queues comprise a queue for memory reference requests to be serviced by a first bank of the off-chip random access memory and a queue for memory reference request to be serviced by a second bank of the off-chip random access memory;

and

wherein the random access memory controller logic comprises logic to enqueue entries for memory reference requests into the queue for memory reference requests to be serviced by the first bank of the off-chip random access memory and into the queue for memory reference request to be serviced by the second bank of the off-chip random access memory based on the memory reference requests.

4. The processor chip of claim 1,

wherein the multiple queues comprise an order queue to store entries for memory reference requests that retains the relative order of memory reference requests received from the multiple programmable units;

and

wherein the random access memory controller logic comprises logic to enqueue entries for memory reference requests received from the multiple programmable units into the order queue to store entries for memory reference requests that retains the relative order of memory reference requests received from the multiple programmable units.

5. The processor chip of claim 4,

wherein the random access memory controller logic comprises logic to enqueue an entry for a memory reference request received from a one of the multiple programmable units in the order queue to store entries for memory reference requests that retains the relative order of memory reference requests received from the multiple programmable units based on data included in the memory reference request.

6. The processor chip of claim 1,

wherein the multiple queues comprise a queue to store entries for memory reference requests including data identifying the memory reference requests as priority requests;

and

wherein the random access memory controller logic comprises logic to enqueue entries for memory reference requests received from the multiple programmable units in the queue to store entries for memory reference requests including data identifying the memory reference requests as priority requests.

7. The processor chip of claim 1,

wherein the random access memory controller logic to select from the enqueued entries comprises random access memory controller logic to select an entry from a same queue as an immediately preceding selected entry based on data included in a memory reference request corresponding to the immediately preceding selected entry.

8. A processor chip, comprising:

multiple programmable units integrated in the processor chip, wherein at least some of the multiple programmable units integrated in the processor chip comprise multi-threaded programmable units having multiple program counters corresponding to multiple threads of program execution;

a random access memory controller integrated in the processor chip to couple to an off-chip random access memory, the random access memory controller coupled to the multiple programmable units integrated in the processor chip, the random access memory controller comprising logic to enqueue entries for memory reference requests received from the multiple programmable units into one of multiple queues and select from the enqueued entries to initiate a memory access operation of the off-chip random access memory,

wherein the multiple queues comprise;

a queue for memory reference requests to be serviced by a first bank of the off-chip random access memory;

a queue for memory reference request to be serviced by a second bank of the off-chip random access memory;

a queue to store entries for memory reference requests that retains the relative order of memory reference requests received from the multiple programmable units.