Lowering voltage for cache memory operation

• US 7,424,663 B2
• Filed: 01/19/2005
• Issued: 09/09/2008
• Est. Priority Date: 01/19/2005
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mehalel, Moty
• Primary Examiner(s): Louis-Jacques; Jacques
• Assistant Examiner(s): Merant; Guerrier
• Application Number:
  US11/039,742
• Publication Number:
  US 20060161831A1
• Time in Patent Office: 1,329 Days
• Field of Search: None
• US Class Current: 714/763
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

Setting a minimum operating voltage (Vcc min) of the cache to a voltage value at which the number of cells that fail in the cache is between approximately 0.1% and approximately 1% of the number of lines in the cache, while the remaining cells continue to function correctly at the voltage value chosen for Vcc min, and compensating for errors produced by memory cells in the cache that fail when operated at the voltage value chosen for Vcc min.

Claims

1. A method of operating a cache comprising volatile memory cells in a mobile processor system, the method comprising:

determining a first voltage value as a minimum operating voltage (Vcc min) of the cache if each of the volatile memory cells functions correctly when the first voltage value is set as Vcc min;

setting a Vcc min of the cache to a second voltage value at which the number of volatile memory cells that fail in the cache is between approximately 0.1% and approximately 1% of the number of lines in the cache, while the remaining volatile memory cells continue to function correctly at the second voltage value chosen for Vcc min; and

compensating for errors produced by volatile memory cells in the cache that fail when operated at the second voltage value chosen for Vcc min to enable operation of the mobile processor system at a reduced Vcc min equal to the second voltage value that is less than the first voltage value.

2. The method of claim 1, wherein compensating for errors produced by memory cells in the cache that fail at the voltage value chosen for Vcc min further comprises compensating for errors produced by memory cells in the cache that fail at the value chosen for the minimum operating voltage using an error correcting code (ECC) unit.

3. The method of claim 2 further comprising compensating for soft errors in memory cells caused by radiation using the ECC unit.

4. The method of claim 2 further comprising producing and storing a signature comprising an indication of the memory cells that fail in the cache.

5. The method of claim 4 wherein the indication further comprises the number of memory cells that failed for each line of the cache.

6. The method of claim 4 wherein the signature further comprises a total of all the memory cells that failed in the cache.

7. The method of claim 6 wherein the error correcting code unit comprises a single bit error correcting code unit.

8. The method of claim 2 further comprising:

for a cache with at least ten thousand cache lines, setting Vcc min to a value at which the number of cells that fail in the cache is approximately one hundred cells.

9. A method in a mobile processor system, the method comprising:

in a cache, the cache further comprising volatile memory cells,

determining a first voltage value as a minimum operating voltage (Vcc min) for the cache if each of the volatile memory cells functions correctly when the second voltage value is set as Vcc min;

setting Vcc min of the cache to a second voltage value that exceeds an estimate of the mean (M) of the operating voltages at which the volatile memory cells fail by between approximately 3.7 and 4.7 times an estimate of the standard deviation (SD) of the operating voltages at which the volatile memory cells fail (M+approximately 3.7*SD<

=Vcc min<

=M+approximately 4.7*SD); and

compensating for errors produced by volatile memory cells in the cache that fail when operated at the second voltage value chosen for the minimum operating voltage using a single bit error correcting code (ECC) unit to enable operation of the mobile processor system at a reduced Vcc min equal to the second voltage value that is less than the first voltage value;

compensating for soft errors in volatile memory cells caused by radiation using the ECC unit; and

producing and storing a signature comprising an indication of the volatile memory cells that fail in the cache.

10. The method of claim 9 further comprising:

estimating the mean of the operating voltage at which a memory cell of the cache fails; and

estimating the standard deviation of the operating voltages at which the memory cells in the cache fail.

11. The method of claim 10 further comprising setting the minimum operating voltage of the cache to a voltage value that exceeds an estimate of the mean (M) of the operating voltages at which the memory cells fail by about 4.2 times an estimate of the standard deviation (SD) of the operating voltages at which the memory cells fail (that is, ˜

M+4.2*SD).

12. A processor comprising:

a cache comprising volatile memory cells;

a voltage source to determine a first voltage value as a minimum operating voltage (Vcc min) of the cache if each of the volatile memory cells functions correctly when the second voltage value is set as Vcc min, and to set Vcc min of the cache to a second voltage value at which the number of volatile memory cells that fail in the cache is between approximately 0.1% and approximately 1% of the number of lines in the cache, while the remaining volatile memory cells continue to function correctly at the second voltage value chosen for Vcc min; and

error compensation logic to compensate for errors produced by volatile memory cells in the cache that fail when operated at the voltage value chosen for Vcc min to enable operation of the mobile processor system at a reduced Vcc min equal to the second voltage value that is less than the first voltage value.

13. The processor of claim 12, wherein the error compensation logic comprises an error correcting code (ECC) unit.

14. The processor of claim 13 wherein the ECC unit is to compensate for soft errors in memory cells caused by radiation.

15. The processor of claim 13 further comprising syndrome logic to produce and store a signature comprising an indication of the memory cells that fail in the cache.

16. The processor of claim 15 wherein the indication further comprises the number of memory cells that failed for each line of the cache.

17. The processor of claim 15 wherein the signature further comprises a total of all the memory cells that failed in the cache.

18. The processor of claim 17 wherein the error correcting code unit comprises a single bit error correcting code unit.

19. The processor of claim 13 wherein, if the cache comprises at least ten thousand cache lines, the voltage source is further to set Vcc min to a value at which the number of cells that fail in the cache is approximately one hundred cells.

20. A processor comprising:

a cache, the cache further comprising volatile memory cells,

a voltage source to determine a first voltage value as a minimum operating voltage (Vcc min) of the cache if each of the volatile memory cells functions correctly when the second voltage value is set as Vcc min, and to set a Vcc min of the cache to a second voltage value that exceeds an estimate of the mean (M) of the operating voltages at which the volatile memory cells fail by between approximately 3.7 and 4.7 times an estimate of the standard deviation (SD) of the operating voltages at which the volatile memory cells fail (M+approximately 3.7*SD<

=Vcc min<

=M+approximately 4.7*SD);

an error correcting code (ECC) unit to compensate for errors produced by volatile memory cells in the cache that fail when operated at the voltage value chosen for the minimum operating voltage, to enable operation of the mobile processor system at a reduced Vcc min equal to the second voltage value that is less than the first voltage value, and to compensate for soft errors in volatile memory cells caused by radiation using the ECC unit; and

syndrome logic to produce and store a signature comprising an indication of the volatile memory cells that fail in the cache.

21. The processor of claim 20 further comprising setting the minimum operating voltage of the cache to a voltage value that exceeds an estimate of the mean (M) of the operating voltages at which the memory cells fail by approximately 4.2 times an estimate of the standard deviation (SD) of the operating voltages at which the memory cells fail (that is, ˜

M+approximately 4.2* SD).

22. A system comprising a processor, the processor comprising:

a cache comprising volatile memory cells;

a voltage source to determine a first voltage value as a minimum operating voltage Vcc min of the cache if each of the volatile memory cells functions correctly when the second voltage value is set as Vcc min, and to set a Vcc min of the cache to a second voltage value at which the number of volatile memory cells that fail in the cache is between approximately 0.1% and approximately 1% of the number of lines in the cache, while the remaining volatile memory cells continue to function correctly at the second voltage value chosen for Vcc min; and

error compensation logic to compensate for errors produced by volatile memory cells in the cache that fail when operated at the voltage value chosen for Vcc min to enable operation of the mobile processor system at a reduced Vcc min equal to the second voltage value that is less than the first voltage value.

23. The system of claim 22, wherein the error compensation logic further comprises an error correcting code (ECC) unit.

24. The system of claim 23 further comprising syndrome logic to produce and store a signature comprising an indication of the memory cells that fail in the cache.

25. The system of claim 24 wherein the indication further comprises the number of memory cells that failed for each line of the cache.

26. The system of claim 24 wherein the signature further comprises a total of all the memory cells that failed in the cache.

27. The system of claim 26 wherein the error correcting code unit comprises a single bit error correcting code unit.

28. The system of claim 23 wherein, if the cache comprises at least ten thousand cache lines, the voltage source is further to set Vcc min to a value at which the number of cells that fail in the cache is approximately one hundred cells.

29. The system of claim 22 wherein the ECC unit is further to compensate for soft errors in memory cells caused by radiation.

30. The system of claim 22 further comprising a dynamic random access memory (DRAM) communicatively coupled to the processor.