Method for implementation of back-illuminated CMOS or CCD imagers

• US 7,425,460 B2
• Filed: 09/13/2005
• Issued: 09/16/2008
• Est. Priority Date: 09/17/2004
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Pain, Bedabrata
• Primary Examiner(s): Tsai; H. Jey
• Application Number:
  US11/226,902
• Publication Number:
  US 20060068586A1
• Time in Patent Office: 1,099 Days
• Field of Search: 438/34, 438/29, 438/32, 438 57- 60, 438/149, 257/E33.068
• US Class Current: 438/29
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1462 Coatings
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20

Abstract

A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

Claims

1. A combined silicon-on-insulator (SOI) and CMOS process to form an array of photodetectors on a wafer, comprising:

providing a SOI wafer comprising an insulator layer buried between a silicon wafer and a device silicon layer;

forming a device layer and interlayer dielectric to form a plurality a photodiodes by processing the device silicon layer through a bulk CMOS process flow;

removing the silicon wafer to expose the insulator layer;

processing the exposed insulator layer to form a passivation layer on the device silicon layer, the passivation layer configured to decrease dark current while keeping quantum efficiency of the photodetectors; and

providing microlenses above the passivation layer, each microlens placed in correspondence of a photodiode.

2. The process of claim 1, wherein the device silicon layer has a thickness from about 3 μ

m to about 10 μ

m.

3. The process of claim 1, wherein a doping concentration of the device silicon layer is inversely proportional to a thickness of a depletion region of the device silicon layer.

4. The process of claim 1, further comprising:

forming an anti-reflection coating between the passivation layer and the microlenses.

5. The process of claim 1, further comprising:

forming color filters between the passivation layer and the microlenses.

6. The process of claim 4, further comprising:

forming color filters between the anti-reflection coating and the microlenses.

7. The process of claim 1, wherein each photodiode of the plurality of photodiodes is connected to a corresponding MOS gate located underneath the photodiode.

8. A combined silicon-on-insulator (SOI) and CMOS process to form an array of photodetectors on a wafer, comprising:

providing a SOI wafer comprising an insulator layer buried between a silicon wafer and a device silicon layer;

forming a device layer and interlayer dielectric to form a plurality a photodiodes by processing the device silicon layer through a bulk CMOS process flow;

removing the silicon wafer to expose the insulator layer;

processing the exposed insulator layer to form a passivation layer on the device silicon layer, the passivation layer configured to decrease dark current while keeping quantum efficiency of the photodetectors; and

providing color filters above the passivation layer, each color filter placed in correspondence of a photodiode.

9. The process of claim 8, further comprising:

forming an anti-reflection coating between the passivation layer and the color filters.

10. The process of claim 8, further comprising:

forming microlenses above the color filters.

11. The process of claim 8, wherein each photodiode of the plurality of photodiodes is connected to a corresponding MOS gate located underneath the photodiode.

12. A combined silicon-on-insulator (SOI) and CMOS process to form an array of photodetectors on a wafer, comprising:

providing a SOI wafer comprising an insulator layer buried between a silicon wafer and a device silicon layer;

forming a device layer and interlayer dielectric to form a plurality a photodiodes by processing the device silicon layer through a bulk CMOS process flow;

removing the silicon wafer to expose the insulator layer;

processing the exposed insulator layer to form a passivation layer on the device silicon layer, the passivation layer configured to decrease dark current while keeping quantum efficiency of the photodetectors; and

providing optical imaging elements above the passivation layer, each optical imaging element placed in correspondence of a photodiode.