Non-volatile memory device and method for fabricating the same

• US 7,425,482 B2
• Filed: 10/12/2005
• Issued: 09/16/2008
• Est. Priority Date: 10/13/2004
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated (SK Hynix Inc.)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Jeong, Yong-Sik
• Primary Examiner(s): Lindsay, Jr.; Walter L.
• Assistant Examiner(s): Ahmadi; Mohsen
• Application Number:
  US11/250,052
• Publication Number:
  US 20060118857A1
• Time in Patent Office: 1,070 Days
• Field of Search: 438/257, 438/201, 438/167, 438/199, 257/E21.209, 257/E21.422, 257/E21.613, 257/E21.659, 257/E21.685, 257/E21.687, 257/315, 257/316
• US Class Current: 438/167
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/44 with a control gate layer also being used as part of the peripheral transistor

Abstract

A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer covering the gate structures and active regions located at each side of the gate structures; forming a second electrode layer over the first insulation layer; and forming a plurality of control gates on the active regions located at each side of the gate structures by performing an etch-back process to the second electrode layer.

Claims

1. A method for fabricating a non-volatile memory device, comprising:

forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate;

forming a first insulation layer covering the gate structures and active regions located at each side of the gate structures;

forming a second electrode layer over the first insulation layer;

forming a plurality of control gates on the active regions located at each side of the gate structures by performing an etch-back process to the second electrode layer; and

performing a silicide process in a cell area including a plurality of control gates on the active regions located at each side of the gate structures.

2. The method of claim 1, wherein each control gate is formed to encompass each side of each gate structure.

3. The method of claim 2, wherein the control gates are connected to each other.

4. The method of claim 3, wherein each control gate is used to connect word lines in the unit of one byte or a predetermined number of bytes.

5. The method of claim 1, wherein the first insulation layer includes a material selected from a group consisting of oxide, nitride and a combination thereof.

6. The method of claim 1, wherein the first electrode layer and the second electrode layer include a material selected from a group consisting of polysilicon, amorphous silicon, tungsten, tungsten silicide, and titanium.

7. The method of claim 1, wherein each gate structure includes a second insulation layer and a third insulation layer, and the first electrode layer is formed between the second and third insulation layers.

8. The method of claim 7, wherein the second insulation layer has a thickness ranging from approximately 70 Å

to approximately 700 Å

.

9. The method of claim 7, wherein the first electrode layer has a thickness ranging from approximately 1,000 Å

to approximately 5,000 Å

.

10. The method of claim 7, wherein the third insulation layer includes a material selected from a group consisting of oxide, nitride and a combination thereof.

11. The method of claim 10, wherein the third insulation layer has a thickness ranging from approximately 500 Å

to approximately 2,000 Å

.

12. A method for fabricating a non-volatile memory device, comprising:

forming a plurality of first gate structures on a first region of a substrate, wherein each gate structure includes a first electrode layer for a floating gate;

forming a first insulation layer on the first gate structures and active regions located at each side of the first gate structure, and a second region of the substrate;

forming a second electrode layer over the first insulation layer;

forming a plurality of control gates on the active regions located at each side of the first gate structures by performing an etch-back process to the second electrode layer, and simultaneously forming a plurality of second gate structures on the second region of the substrate using a photoresist pattern as an etch mask; and

forming a silicide process in a cell area including a plurality of control gates on the active regions located at each side of the gate structures.

13. The method of claim 12, wherein the first insulation layer and the fourth insulation layer include a material selected from a group consisting of oxide, nitride and combination thereof.

14. The method of claim 12, wherein the first electrode layer and the second electrode layer include a material selected from a group consisting of polysilicon, amorphous silicon, tungsten, tungsten silicide, and titanium.

15. The method of claim 12, wherein the first gate structures are used for storing data and the second gate structures are used for a peripheral circuit.

16. The method of claim 12, wherein the forming of the second gate structure includes:

forming the photoresist pattern on a predetermined portion of the second electrode layer on the second region of the substrate; and

patterning the second electrode layer using the photoresist pattern as the etch mask to form the second gate structures on the second region of the substrate.

17. The method of claim 12, wherein the control gates are connected to each other.

18. The method of claim 17, wherein each control gate is used to connect word lines in the unit of one byte or a predetermined number of bytes.

19. The method of claim 12, wherein each first gate structure includes a second insulation layer and a third insulation layer, and the first electrode layer is formed between the second and third insulation layers.

20. The method of claim 19, wherein the second insulation layer has a thickness ranging from approximately 70 Å

to approximately 100 Å

.

21. The method of claim 19, wherein the first electrode layer has a thickness ranging from approximately 1,000 Å

to approximately 5,000 Å

.

22. The method of claim 19, wherein the third insulation layer includes a material selected from a group consisting of oxide, nitride and a combination thereof.

23. The method of claim 22, wherein the third insulation layer has a thickness ranging from approximately 500 Å

to approximately 2,000 Å

.