Device and method for sensing programming status of non-volatile memory elements

• US 7,426,142 B1
• Filed: 05/01/2006
• Issued: 09/16/2008
• Est. Priority Date: 05/05/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Stansell, Galen E., Cewe, Tomasz
• Primary Examiner(s): Lam, David
• Application Number:
  US11/415,694
• Time in Patent Office: 869 Days
• Field of Search: 365/185.21, 365/201, 365/189.07, 365/225.7, 365/210, 365/189.05
• US Class Current: 365/185.21
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A test circuit can test a status of a group of non-volatile elements. A current flowing to the group of non-volatile elements can be compared against a reference value. If the current is determined to be outside of a predetermined range, the non-volatile elements can be determined to be programmed. In particular embodiments, non-volatile elements can be sections of differential one-time programmable anti-fuse latch memory elements.

Claims

1. A method for determining the state of non-volatile memory elements in an integrated circuit, comprising the steps of:

a) enabling a current path to an array of non-volatile memory elements;

b) determining a current drawn by the array;

c) if the current drawn by the array is outside of a first predetermined limit, generating an indication that the array is programmed; and

d) if the current drawn by the array is inside a second predetermined limit, generating an indication that the array is not programmed.

2. The method of claim 1, wherein:

enabling the current path includes providing a low impedance path between a high power supply voltage node and the array.

3. The method of claim 1, wherein:

enabling the current path includes providing a low impedance path between a low power supply voltage node and the array.

4. The method of claim 1, wherein:

determining the current drawn by the array includes generating a test voltage with a resistance that receives the current drawn by the array and comparing the test voltage to a reference voltage.

5. The method of claim 1, wherein:

generating the indication that the array is programmed includes driving an indication signal to a first predetermined value, and outputting the indication signal from the integrated circuit; and

generating the indication that the array is not programmed includes driving the indication signal to a second predetermined value, and outputting the indication signal from the integrated circuit.

6. The method of claim 1, further including:

each non-volatile memory element includes a non-volatile storage element and a volatile storage element;

if the indication is generated that the array is not programmed, initializing the volatile storage elements of the non-volatile memory elements of the array to the same logic value; and

if the indication is generated that the array is programmed, loading logic states of the non-volatile storage elements of each memory element into the corresponding volatile storage element of the memory element.

7. The method of claim 1, further including:

each non-volatile memory element includes a non-volatile storage element and a volatile storage element and the method further includes

e) setting an array address to a first address;

f) accessing a first array of non-volatile memory elements according to the array address;

g) performing steps a) to d) on the first array;

h) if the indication is generated that the array is programmed,

increment the array address and repeat steps f) and g) until an unprogrammed array is found or the array address reaches a last address plus the increment value,

initializing the volatile storage elements with the corresponding non-volatile element data for all arrays indicated by the last address minus the increment value.

8. The method of claim 1, wherein:

each non-volatile memory element includes a non-volatile storage element and a volatile storage element; and

a) enabling the current path to an array of non-volatile memory elements includes providing a low impedance path between each non-volatile storage element of the array and the corresponding volatile storage element.

9. The method of claim 1, wherein:

the first predetermined limit is the same as the second predetermined limit.

10. A circuit for determining the state of a block of non-volatile (NV) memory elements, comprising:

at least one block of NV memory elements having a first power supply node that provides power to at least each NV memory element of the block;

a sense impedance that receives a current corresponding to a power supply current drawn by the block of NV memory elements; and

a comparator having at least one input coupled to the sense impedance, the comparator generating a programmed indication when the current drawn by the block of NV memory elements exceeds a predetermined limit.

11. The circuit of claim 10, wherein:

each NV memory element comprises a non-volatile storage element coupled to a volatile storage element.

12. The circuit of claim 11, wherein:

the non-volatile storage element comprises at least one anti-fuse device and the volatile storage element comprises a latch.

13. The circuit of claim 12, wherein:

the non-volatile storage element comprises at least two anti-fuse device coupled in parallel to the power supply node.

14. The circuit of claim 10, further including:

a test controllable impedance path coupled between the first power supply node and the block of NV memory elements;

a supply controllable impedance path coupled between the first power supply node and the block of NV memory elements in parallel with the test controllable impedance path;

the sense impedance is coupled between the test controllable impedance path and the block of NV memory elements; and

the comparator has a first input coupled to a node between the sense impedance and the block of NV memory elements and a second input coupled to receive at least one reference voltage.

15. The circuit of claim 14, wherein:

the first power supply node is a high power supply node and the test controllable impedance path and supply controllable impedance path comprise p-channel insulated gate field effect transistors.

16. The circuit of claim 14, wherein:

the first power supply node is a low power supply node and the test controllable impedance path and supply controllable impedance path comprise n-channel insulated gate field effect transistors.

17. The test circuit of claim 14, further including:

a control logic circuit that provides control signals to the test controllable impedance path, the supply controllable impedance path, and the block of NV memory elements, and is coupled to receive an output of the comparator.

18. The test circuit of claim 10, further including:

a test supply transistor having a controllable impedance path coupled between the first power supply node and the block of NV memory elements;

a test mirror transistor having a controllable impedance path coupled in parallel with the controllable impedance path of the supply transistor, and a control terminal coupled to the control terminal of the supply transistor to mirror the current provided by the test supply transistor; and

the sense impedance is coupled to the controllable impedance path of the test mirror transistor.

19. An integrated circuit having non-volatile memory elements with testable states, comprising:

a plurality of memory element blocks, each block comprising a plurality of nonvolatile storage elements electrically connectable to corresponding latch circuits according to a load signal, each nonvolatile storage element comprising a volatile latch and a first anti-fuse device coupled to a first node of the volatile latch and a second anti-fuse device coupled to the second node of the volatile latch;

a supply control device that enables a current path to the memory element blocks; and

a current measuring circuit that measures current drawn by a memory element block in response to the activation of the load signal of the memory element block and activates a programmed block status indication that indicates a memory element block is programmed when the current drawn by the memory element block is outside of a predetermined limit.

20. The integrated circuit of claim 19, wherein:

the current measuring circuit, comprises

a test resistance coupled between the supply control device and the plurality of memory element blocks, and

a comparator circuit having a first input coupled to the test resistance and a second input coupled to receive at least one reference voltage.