Switch for bus optimization

• US 7,426,602 B2
• Filed: 01/07/2005
• Issued: 09/16/2008
• Est. Priority Date: 01/08/2004
• Status: Expired due to Fees

• Current Assignee: Topside Research LLC
• Original Assignee: Topside Research LLC
• Inventors: Wong, Ken, Haywood, Chris, Stewart, Heath, Rappoport, Adam, Shaikli, Nadim, Reiner, Thomas, Vuong, Bao, de la Garrigue, Mike
• Primary Examiner(s): Auve; Glenn A.
• Assistant Examiner(s): Vu; Trisha
• Application Number:
  US11/031,420
• Publication Number:
  US 20050154804A1
• Time in Patent Office: 1,348 Days
• Field of Search: 710/316, 710/317, 710/29, 710/104, 710/105
• US Class Current: 710/317
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Claims

1. A switch, comprising:

a plurality of port units, each port unit including

an ingress portion and an egress portion, the ingress portion comprising an input buffer, an input queue and input logic, and the egress portion comprising an output pipe; and

a control matrix coupled between the plurality of port units to control bus communications between the plurality of port units,

wherein the control matrix performs prioritization, allocation, and virtual channel arbitration pursuant to a PCI Express specification to determine the sequence in which data units are sent from the ingress portions of the port units to the output pipes, and

wherein data units are not reordered after being sent from the control matrix to the output pipes.

2. The switch of claim 1 wherein the control matrix performs the functionality of buffers and logic traditionally included in the egress portion of the port units.

3. The switch of claim 1 wherein the input queue includes a posted transaction queue, a non-posted transaction queue and a completion transaction queue.

4. The switch of claim 1 implemented on a single field programmable gate array.

5. The switch of claim 1 wherein at least two of the port units are coupled with a device.

6. The switch of claim 5 wherein the device includes one or more selected from the group comprising:

a graphics card, a sound card, a network communications unit, a computer peripheral, a computer chip set, and a processor.

7. The switch of claim 1 wherein the control matrix performs egress flow control and deadlock avoidance pursuant to a PCI Express specification.

8. A computer comprising:

a bus switch including

a plurality of port units, each port unit further comprising

an ingress portion comprising an input buffer, an input queue and input logic

an egress portion comprising an output pipe

a control matrix coupled between the plurality of port units to control bus communications between the plurality of port units,

wherein the control matrix performs prioritization, allocation, and virtual channel arbitration pursuant to a PCI Express specification to determine the sequence in which data units are sent from the ingress portions of the port units to the output pipes,

wherein data units are not reordered after being sent from the control matrix to the output pipes, and

wherein at least two of the port units are each coupled with a device selected from the group comprising;

a graphics card, a sound card, a network communications unit, a computer peripheral, a computer chip set, and the processor.

9. The computer of claim 8 wherein the control matrix performs the functionality of buffers and logic traditionally included in the egress portion of the port units.

10. The computer of claim 8 wherein the input queue includes a posted transaction queue, a non-posted transaction queue and a completion transaction queue.

11. A switch, comprising:

a plurality of port units, each port unit functional as both an input port and an output port, each port unit having

an ingress portion for supporting input port functionality and comprising an input buffer, an input queue for storing data units from the input buffer, and input logic coupled to the input queue for selecting an available data unit from the input queue, and

an egress portion for supporting output port functionality and consisting essentially of an output pipe for outputting data units without reordering them;

control logic coupled to the port units to control communication of data units from the ingress portion of a given port unit to the egress portion of a different port unit, the control logic operative to

perform a look ahead function that is applied to the selection process of the respective input logic of the port units so that data units are directly passed from the ingress portions of the input ports to the output pipes of the output ports,

provide ingress and egress reordering functions for the port units in a single, interlaced matrix, and

evaluate and set a sequence of data units output through the output pipes in accordance with rules for arbitration, prioritization, reordering, and contention management.

12. The switch of claim 11, the control logic comprising:

egress flow control gating logic

port arbitration logic

deadlock avoidance logic.

13. The switch of claim 11 wherein the input queue includes a posted transaction queue, a non-posted transaction queue and a completion transaction queue.

14. The switch of claim 11 implemented on a single field programmable gate array.

15. The switch of claim 11 wherein the input logic within the port units and the control logic collectively perform ingress and egress reordering, egress flow control, contention management, deadlock avoidance, and virtual channel arbitration pursuant to a PCI Express specification.

16. A method of switching data units, comprising:

receiving data units in the ingress portions of a plurality of port units, the ingress portion of each port unit receiving data units in an input buffer and storing data units from the input buffer in an input queue,

control logic controlling communication of data units from the ingress portion of a given port unit to the egress portion of a different port unit, the control logic

performing a look ahead function that is applied to the selection process of the respective input logic of the port units so that data units are directly passed from the ingress portions of the input ports to the output pipes of the output ports,

providing ingress and egress reordering functions for the port units in a single, interlaced matrix, and

evaluating and setting a sequence of data units to be output through egress portions of the plurality of port units in accordance with rules for arbitration, prioritization, reordering, and contention management,

input logic within the ingress portions of the plurality of port units selecting data units from the respective input queues in accordance with the sequence of data units set by the control logic,

transferring the selected data units to the egress portions of other port units of the plurality of port units, the egress portion of each port unit consisting essentially of an output pipe for outputting data units without reordering them,

outputting data units from the output pipes of the ports units in accordance with the sequence set by the control logic.

17. The method of switching data units of claim 16, the control logic further performing egress flow control gating and deadlock avoidance.

18. The method of switching data units of claim 16 wherein each input queue includes a posted transaction queue, a non-posted transaction queue and a completion transaction queue.

19. The method of switching data units of claim 16 wherein the input logic within the port units and the control logic collectively perform ingress and egress reordering, egress flow control, contention management, deadlock avoidance, and virtual channel arbitration pursuant to a PCI Express specification.