Memory bus arbitration using memory bank readiness

• US 7,426,603 B2
• Filed: 08/04/2006
• Issued: 09/16/2008
• Est. Priority Date: 08/08/2001
• Status: Expired due to Term

• Current Assignee: Computer Circuit Operations LLC
• Original Assignee: Pasternak Solutions LLC (Intellectual Ventures LLC)
• Inventors: Purcell, Stephen Clark, Kimura, Scott
• Primary Examiner(s): SONG, HUA JASMINE
• Application Number:
  US11/499,015
• Publication Number:
  US 20060271724A1
• Time in Patent Office: 774 Days
• Field of Search: 711/5, 711/151, 711/158, 710/39, 710/240, 710/244
• US Class Current: 711/5
• CPC Class Codes: G06F 13/1626 by reordering requests
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.

Claims

1. An apparatus comprising:

a memory bus configured to transmit N memory transaction items at a time;

a queue configured to store more than N memory transaction items;

a memory circuit coupled to the memory bus, wherein the memory circuit comprises more than N memory banks, and wherein each memory transaction item is addressed to a memory bank;

a multiplexer comprising at least N multiplexer inputs and a multiplexer output, wherein each multiplexer input is coupled to one of the memory transaction items, and wherein the multiplexer output is coupled to the memory bus;

a state machine coupled to the multiplexer output, wherein the state machine is configured to generate a bank readiness signal that identifies the readiness of a memory bank to accept a memory transaction item that is addressed to the memory bank; and

an arbiter controller coupled to the state machine and a selection input of the multiplexer, wherein the arbiter controller is configured to activate the selection input of the multiplexer to select a memory transaction item to transmit from the queue to the addressed memory bank that is identified by the bank readiness signal.

2. The apparatus of claim 1 wherein the arbiter controller is further configured to select the memory transaction item to transmit from the queue to the memory bank based on a priority when more than one memory transaction items addressed to the same memory bank are identified by a bank readiness signal.

3. The apparatus of claim 2 wherein the arbiter controller is further configured to select the oldest memory transaction item to transmit from the queue to the memory.

4. The apparatus of claim 2 wherein each memory transaction item is stored in a request station in the queue, and further wherein the request station identifies the priority associated with the memory transaction item.

5. The apparatus of claim 1, wherein the state machine is further configured to reset the bank readiness signal for a memory bank when a memory transaction item is transmitted to the memory bank.

6. An apparatus comprising:

a queue circuit comprising a plurality of request stations arranged to store memory transactions, wherein each request station is coupled to a memory transaction request line;

a memory transaction multiplexer circuit comprising a plurality of multiplexer inputs, a multiplexer output, and a multiplexer selection input, wherein each multiplexer input is coupled to one of the memory transaction request lines; and

a memory circuit coupled to the multiplexer output, wherein the memory circuit comprises a plurality of memory banks, wherein each memory bank is configured to store a memory transaction transmitted from the queue circuit and addressed to the memory bank; and

a state machine circuit comprising a state machine input coupled to the multiplexer output and a state machine output coupled to the multiplexer selection input, wherein the state machine is configured to generate a bank readiness signal that identifies the readiness of a memory bank to accept a memory transaction that is addressed to the memory bank.

7. The apparatus of claim 6, wherein the state machine is further configured to reset the bank readiness signal for a memory bank when a memory transaction is transmitted to the memory bank.

8. An apparatus comprising:

a queue circuit comprising a plurality of request stations arranged to store memory transactions, wherein each request station is coupled to a memory transaction request line;

a memory transaction multiplexer circuit comprising a plurality of multiplexer inputs, a multiplexer output, and a multiplexer selection input, wherein each multiplexer input is coupled to one of the memory transaction request lines;

a memory circuit coupled to the multiplexer output, wherein the memory circuit comprises a plurality of memory banks, wherein each memory bank is configured to store a memory transaction transmitted from the queue circuit and addressed to the memory bank;

a state machine comprising a state machine input coupled to the multiplexer output and a plurality of state machine outputs, wherein the state machine is configured to generate a bank readiness signal that identifies the readiness of a memory bank to accept a memory transaction that is addressed to the memory bank; and

an arbiter controller comprising a plurality of arbiter inputs coupled to the plurality of state machine outputs and an arbiter output coupled to the multiplexer selection input, wherein the arbiter controller is configured to activate the multiplexer selection input to select a memory transaction to transmit from the queue circuit to the addressed memory bank that is identified by the bank readiness signal.

9. The apparatus of claim 8, wherein the state machine is further configured to reset the bank readiness signal for a memory bank when a memory transaction is transmitted to the memory bank.

10. The apparatus of claim 8, wherein the arbiter controller is further configured to select a memory transaction to transmit from the queue circuit to the memory bank based on a priority when more than one memory transactions addressed to the same memory bank are identified by a bank readiness signal.

11. The apparatus of claim 10, wherein the arbiter controller is further configured to select the oldest memory transaction item to transmit from the queue to the memory.

12. The apparatus of claim 10, wherein the priority associated with the memory transaction is identified by the request station in which the memory transaction is stored.

13. The apparatus of claim 8, wherein the state machine is further configured to reset the bank readiness signal for a memory bank when a memory transaction is transmitted to the memory bank.

14. A method of using a multiplexer to manage the transmission of a plurality of memory transactions to a memory having a plurality of memory banks, the multiplexer comprising a plurality of multiplexer inputs for receiving the plurality of memory transactions and a multiplexer output for sending each of the plurality of memory transactions to the memory, the method comprising:

receiving a plurality of memory transactions at the multiplexer inputs, wherein each memory transaction is addressed to a corresponding memory bank;

associating a priority with each received memory transaction;

generating a plurality of bank readiness signals indicating the readiness of each memory bank available to accept a memory transaction, wherein the plurality of bank readiness signals are based on the plurality of memory transactions at the multiplexer inputs and the multiplexer output; and

sending each of the plurality of memory transactions to its corresponding one of the plurality of memory banks via the multiplexer output based on the associated priorities and the bank readiness signals.

15. The method of claim 14, wherein the priority associated with each memory transaction is based on the order in which the memory transaction was received.

16. The method of claim 14, wherein the priority associated with each memory transaction is based on the memory transaction'"'"'s position in a queue.

17. The method of claim 14, wherein generating a plurality of bank readiness signals indicating the readiness of each memory bank to accept a memory transaction comprises tracking the availability of memory banks and monitoring the memory addresses of the received memory transactions.

18. The method of claim 14, further comprising:

after sending one of the plurality of memory transactions to its corresponding one of the plurality of memory banks, clearing the bank readiness signal corresponding to the one memory bank to indicate that the memory bank is not available to accept a memory transaction.

19. The method of claim 18, further comprising:

after a predetermined period of time, generating a bank readiness signal corresponding to the one memory bank to indicate that the memory bank is available to accept a memory transaction.

20. A machine-readable storage device with instructions to cause a microprocessor to perform the steps of:

receiving a plurality of memory transactions at a multiplexer, wherein the multiplexer manages the transmission of the plurality of memory transactions to a memory having a plurality of memory banks, the multiplexer comprising a plurality of multiplexer inputs and a multiplexer output, wherein the plurality of memory transactions is received at the multiplexer inputs, and wherein each memory transaction is addressed to a corresponding memory bank;

associating a priority with each received memory transaction;

generating a plurality of bank readiness signals indicating the readiness of each memory bank available to accept a memory transaction, wherein the plurality of bank readiness signals are based on the plurality of memory transactions at the multiplexer inputs and the multiplexer output; and

sending each of the plurality of memory transactions to its corresponding one of the plurality of memory banks via the multiplexer output based on the associated priorities and the bank readiness signals.

21. The machine-readable storage device of claim 20, wherein the priority associated with each memory transaction is based on the order in which the memory transaction was received.

22. The machine-readable storage device of claim 20, wherein the priority associated with each memory transaction is based on the memory transaction'"'"'s position in a queue.

23. The machine-readable storage device of claim 20, wherein generating a plurality of bank readiness signals indicating the readiness of each memory bank to accept a memory transaction comprises tracking the availability of memory banks and monitoring the memory addresses of the received memory transactions.

24. The machine-readable storage device of claim 20, further comprising:

after sending one of the plurality of memory transactions to its corresponding one of the plurality of memory banks, clearing the bank readiness signal corresponding to the one memory bank to indicate that the memory bank is not available to accept a memory transaction.

25. The machine-readable storage device of claim 24, further comprising:

after a predetermined period of time, generating a bank readiness signal corresponding to the one memory bank to indicate that the memory bank is available to accept a memory transaction.