Top layers of metal for high performance IC's

• US 7,427,560 B2
• Filed: 10/31/2007
• Issued: 09/23/2008
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): LOUIE, WAI SING
• Application Number:
  US11/930,682
• Publication Number:
  US 20080050909A1
• Time in Patent Office: 328 Days
• Field of Search: 438/622, 438/623, 438/624, 438/637
• US Class Current: 438/622
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Claims

1. A method for fabricating a chip, comprising:

providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, wherein said first opening has a transverse dimension between 0.1 and 50 micrometers, and a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separate from each other;

forming a first polymer layer over said passivation layer, a third opening in said first polymer layer exposing said first pad, and a fourth opening in said first polymer layer exposing said second pad, wherein said first polymer layer has a thickness of between 2 and 50 micrometers and greater than that of said passivation layer, that of said first dielectric layer and that of said second dielectric layer; and

forming a second metallization structure over said layer and over said first and second pads, wherein said first pad is connected to said second pad through said first opening, said third opening, said second metallization structure, said fourth opening and said second opening, wherein said forming said second metallization structure comprises sputtering an adhesion layer over said first polymer layer and over said first and second pads, wherein said adhesion layer has a thickness between 0.01 and 3 micrometers, sputtering a seed layer over said adhesion layer, wherein said seed layer has a thickness between 0.05 and 3 micrometers, forming a photoresist layer on said seed layer, wherein a fifth opening in said photoresist layer exposes said seed layer, and wherein said photoresist layer has a thickness between 2 and 100 micrometers, electroplating a first copper layer on said seed layer exposed by said fifth opening, wherein said first copper layer has a thickness between 2 and 100 micrometers, removing said photoresist layer, and removing said seed layer and said adhesion layer using said first copper layer as an etch mask.

2. The method of claim 1, wherein said sputtering said adhesion layer comprises sputtering a titanium-tungsten alloy (TiW).

3. The method of claim 1, wherein said sputtering said seed layer comprises sputtering a second copper layer.

4. The method of claim 1, wherein said forming said first polymer layer comprises

5. The method of claim 1, wherein said forming said first polymer layer comprises forming a benzocyclobutene (BCB) layer.

6. The method of claim 1, after said forming said second metallization structures, further comprising forming a second polymer layer over said second metallization structure.

7. The method of claim 6, wherein said forming said second polymer layer comprises forming a polyimide layer.

8. The method of claim 1, wherein said passivation layer comprises a topmost nitride layer of said chip and a topmost oxide layer of said chip.

9. The method of claim 1, wherein said first copper layer has a thickness greater than those of said first and second metal layers.

10. A method for fabricating a chip, comprising:

providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, wherein said first opening has a transverse dimension between 0.1 and 50 micrometers, and a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separate from each other;

forming a first polymer layer over said passivation layer, a third opening in said first polymer layer exposing said first pad, and a fourth opening in said first polymer layer exposing said second pad, wherein said first polymer layer has a thickness between 2 and 50 micrometers and greater than that of said passivation layer, that of said first dielectric layer and that of said second dielectric layer; and

forming a second metallization structure over said first polymer layer and over said first and second pads, wherein said first pad is connected to said second pad through said first opening, said third opening, said second metallization structure, said fourth opening and said second opening, wherein said forming said second metallization structure comprises sputtering an adhesion layer over said first polymer layer and over said first and second pads, wherein said adhesion layer has a thickness between 0.01 and 3 micrometers, sputtering a seed layer over said adhesion layer wherein said seed layer has a thickness between 0.05 and 3 micrometers, forming a photoresist layer on said seed layer, wherein a fifth opening in said photoresist layer exposes said seed layer, and wherein said photoresist layer has a thickness between 2 and 100 micrometers, electroplating a first gold layer on said seed layer exposed by said fifth opening, wherein said first gold layer has a thickness between 2 and 100 micrometers, removing said photoresist layer, and removing said seed layer and said adhesion layer using said first gold layer as an etch mask.

11. The method of claim 10, wherein said sputtering said adhesion layer comprises sputtering a titanium-tungsten alloy (TiW).

12. The method of claim 10, wherein said sputtering said seed layer comprises sputtering a second gold layer.

13. The method of claim 10, wherein said forming said first polymer layer comprises forming a polyimide layer.

14. The method of claim 10, wherein said forming said first polymer layer comprises forming a benzocyclobutene (BCB) layer.

15. The method of claim 10, after said forming said second metallization structure, further comprising forming a second polymer layer over said second metallization structure.

16. The method of claim 15, wherein said forming said second polymer layer comprises forming a polyimide layer.

17. The method of claim 10, wherein said passivation layer comprises a topmost nitride layer of said chip and a topmost oxide layer of said chip.

18. The method of claim 10, wherein said first gold layer has a thickness greater than those of said first and second metal layers.