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Top layers of metal for high performance IC's

  • US 7,427,560 B2
  • Filed: 10/31/2007
  • Issued: 09/23/2008
  • Est. Priority Date: 12/21/1998
  • Status: Expired due to Fees
First Claim
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1. A method for fabricating a chip, comprising:

  • providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, wherein said first opening has a transverse dimension between 0.1 and 50 micrometers, and a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separate from each other;

    forming a first polymer layer over said passivation layer, a third opening in said first polymer layer exposing said first pad, and a fourth opening in said first polymer layer exposing said second pad, wherein said first polymer layer has a thickness of between 2 and 50 micrometers and greater than that of said passivation layer, that of said first dielectric layer and that of said second dielectric layer; and

    forming a second metallization structure over said layer and over said first and second pads, wherein said first pad is connected to said second pad through said first opening, said third opening, said second metallization structure, said fourth opening and said second opening, wherein said forming said second metallization structure comprises sputtering an adhesion layer over said first polymer layer and over said first and second pads, wherein said adhesion layer has a thickness between 0.01 and 3 micrometers, sputtering a seed layer over said adhesion layer, wherein said seed layer has a thickness between 0.05 and 3 micrometers, forming a photoresist layer on said seed layer, wherein a fifth opening in said photoresist layer exposes said seed layer, and wherein said photoresist layer has a thickness between 2 and 100 micrometers, electroplating a first copper layer on said seed layer exposed by said fifth opening, wherein said first copper layer has a thickness between 2 and 100 micrometers, removing said photoresist layer, and removing said seed layer and said adhesion layer using said first copper layer as an etch mask.

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