Thin-film transistor and methods

• US 7,427,776 B2
• Filed: 10/07/2004
• Issued: 09/23/2008
• Est. Priority Date: 10/07/2004
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.), Oregon State University (Oregon University System)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Hoffman, Randy, Mardilovich, Peter, Chiang, Hai
• Primary Examiner(s): Wilczewski; M.
• Assistant Examiner(s): Chiu; Tsz K
• Application Number:
  US10/961,507
• Publication Number:
  US 20060079037A1
• Time in Patent Office: 1,447 Days
• Field of Search: 257/40, 257/213, 257/43, 257/39, 257/59, 257/347
• US Class Current: 257/59
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin-film transistor (TFT) is fabricated by providing a substrate, depositing and patterning a metal gate, anodizing the patterned metal gate to form a gate dielectric on the metal gate, depositing and patterning a channel layer comprising a multi-cation oxide over at least a portion of the gate dielectric, and depositing and patterning a conductive source and conductive drain spaced apart from each other and disposed in contact with the channel layer.

Claims

1. A method for fabricating a thin-film transistor (TFT), comprising the steps of:

a) providing a substrate,

b) depositing and patterning a metal gate adapted to be anodized,

c) anodizing the patterned metal gate to form a gate dielectric on the metal gate,

d) depositing and patterning a channel layer comprising a multi-cation oxide inorganic material over at least a portion of the gate dielectric, and

e) depositing and patterning a conductive source and conductive drain spaced apart from each other and disposed in contact with the channel layer.

2. The method of claim 1, further comprising the step of annealing after forming a gate dielectric on the metal gate.

3. The method of claim 1, further comprising the step of annealing after depositing the channel layer comprising a multi-cation oxide.

4. The method of claim 1, further comprising the step of annealing after patteming the channel layer comprising a multi-cation oxide.

5. The method of claim 1, wherein the substrate provided is flexible.

6. The method of claim 1, wherein the substrate provided is substantially transparent.

7. The method of claim 1, wherein the substrate provided comprises a polyimide.

8. The method of claim 1, wherein the steps are performed at temperatures equal to or less than about 400 degrees C.

9. The method of claim 1, wherein the steps are performed at temperatures equal to or less than about 125 degrees C.

10. The method of claim 1, wherein the steps are performed in the order recited.

11. The method of claim 1, wherein the multi-cation oxide comprises a mixed oxide of two or more cations of groups 11, 12, 13, 14, and 15 of the periodic table.

12. The method of claim 1, wherein the multi-cation oxide comprises a mixed oxide including two or more cations selected from the list consisting of copper, silver, lead, germanium, antimony, gallium, cadmium, zinc, indium, and tin.

13. The method of claim 1, wherein the muiti-cation oxide comprises a mixed oxide including two or more cations selected from the list consisting of gallium, cadmium, zinc, indium, and tin.

14. The method of claim 1, wherein the multi-cation oxide comprises zinc-indium oxide.

15. The method of claim 14, wherein the zinc-indium oxide has an atomic ratio of zinc to indium between about 1:

1 and about 1;

8.

16. The method of claim 14, wherein the zinc-indium oxide has an atomic ratio of zinc to indium between about 1:

2 and about 1;

6.

17. The method of claim 14, wherein the zinc-indium oxide has an atomic ratio of zinc to indium of about 1:

4.

18. The method of claim 1, wherein the multi-cation oxide is amorphous.

19. The method of claim 1, wherein step b) of depositing and patterning a metal gate adapted to be anodized comprises depositing a metal selected from the list consisting of aluminum, tantalum, titanium, tungsten, and alloys thereof.

20. The method of claim 1, wherein step b) of depositing and patterning a metal gate adapted to be anodized comprises depositing a metal selected tram the list consisting of aluminum, tantalum, and alloys thereof.

21. The method of claim 1, wherein step b) of depositing and patterning a metal gate adapted to be anodized comprises depositing aluminum.

22. The method of claim 1, wherein the step d) of depositing and patterning a channel layer comprising a multi-cation oxide includes sputtering the multi-cation oxide over at least a portion of the gate dielectric.

23. The method of claim 22, wherein the sputtering is performed at temperatures equal to or less than about 400 degrees C.

24. The method of claim 22, wherein the sputtering is performed at temperatures equal to or less than about 125 degrees C.

25. The method of claim 22, wherein the multi-cation oxide comprises zinc-indium oxide.

26. The method of claim 22. wherein the sputtering is performed by sputtering from a target comprising the multi-cation oxide.

27. The method of claim 22, wherein the sputtering is performed by reactively sputtering from a metallic target comprising an alloy of the selected metal catians.

28. The method of claim 22, wherein the sputtering is performed by co-sputtering from two or more targets comprising oxides of different cations.

29. The method of claim 22, wherein the sputtering is performed by reactively co-sputtering from two or more metallic targets comprising different metal cations.

30. The method of claim 1, wherein step e) of depositing and patterning a conductive source and conductive drain comprises depositing and patterning indium-tin oxide (ITO).

31. A method for fabricating a thin-film transistor (TFT), comprising the steps of:

a) providing a flexible substrate,

b) depositing on the flexible substrate a metal film adapted to be anodized and patterning a metal gate,

c) anodizing the patterned metal gate to form a gate dielectric on the metal gate,

d) optionally annealing,

e) depositing and patterning a channel layer comprising zinc-indium oxide,

f) optionally annealing,

g) depositing and patterning a conductive source and conductive drain comprising indium-tin oxide (ITO), and

h) depositing and patterning conductive contact pads electrically coupled to the metal gate, the conductive source, and the conductive drain respectively.

32. The method of claim 31, wherein the steps are performed in the order recited.

33. The method of claim 31, wherein the metal film adapted to be anodized comprises aluminum.

34. A thin-film transistor formed on a substrate, the thin-film transistor comprising:

a) a metallic gate disposed on the substrate,

b) a gate dielectric formed by anodization of the metallic gate and covering the metallic gate,

c) a channel comprising a multi-cation oxide inorganic material disposed on at least a portion of the gate dielectric, and

d) a conductive source and a conductive drain, both contiguous with the channel and spaced apart from each other.

35. The thin-film transistor of claim 34, wherein the substrate comprises a flexible film.

36. The thin-film transistor of claim 34, wherein the substrate is substantially transparent.

37. The thin-film transistor of claim 34, wherein the substrate comprises a polyimide.

38. The thin-film transistor of claim 34, wherein the multi-cation oxide comprises a mixed oxide of two or more cations of the groups 11, 12, 13, 14, and 15 of the periodic table.

39. The thin-film transistor of claim 34, wherein the multi-cation oxide comprises a mixed oxide including two or more cations selected from the list consisting of copper, silver, lead, germanium, antimony, gallium, cadmium, zinc, indium, tin, and combinations thereof.

40. The thin-film transistor of claim 34, wherein the multi-cation oxide comprises a mixed oxide including two or more cations selected from the list consisting of gallium, cadmium, zinc, indium, and tin.

41. The thin-film transistor of claim 34, wherein the multi-cation oxide comprises zinc-indium oxide.

42. The thin-film transistor of claim 41, wherein the zinc-indium oxide has an atomic ratio of zinc to indium between about 1:

1 and about 1;

8.

43. The thin-film transistor of claim 41, wherein the zinc-indium oxide has an atomic ratio of zinc to indium between about 1:

2 and about 1;

6.

44. The thin-film transistor of claim 41, wherein the zinc-indium oxide has an atomic ratio of zinc to indium of about 1:

4.

45. The thin-film transistor of claim 34, wherein the multi-cation oxide is amorphous.

46. The thin-film transistor of claim 34, wherein the metallic gate comprises a metal selected from the list consisting of aluminum, tantalum, titanium, tungsten, and alloys thereof.

47. The thin-film transistor of claim 34, wherein the metallic gate comprises a metal selected from the list consisting of aluminum, tantalum, and alloys thereof.

48. The thin-film transistor of claim 34, wherein the metallic gate comprises aluminum.

49. The thin-film transistor of claim 34, wherein the gate dielectric comprises aluminum oxide.

50. The thin-film transistor of claim 34, wherein the gate dielectric comprises tantalum oxide.

51. The thin-film transistor of claim 34, wherein the conductive source comprises indium-tin oxide (ITO).

52. The thin-film transistor of claim 51, wherein the indium-tin oxide (ITO) of the conductive source is substantially transparent.

53. The thin-film transistor of claim 34, wherein the conductive drain comprises indium-tin oxide (ITO).

54. The thin-film transistor of claim 53, wherein the indium-tin oxide (ITO) of the conductive drain is substantially transparent.

55. The thin-film transistor of claim 34, wherein both the conductive source and conductive drain comprise substantially transparent indium-tin oxide (ITO).

56. An integrated circuit comprising the thin-film transistor of claim 34.

57. A display comprising the thin-film transistor of claim 34.

58. The thin-film transistor of claim 34, wherein each element and material thereof and their combination have the properties resulting from exposure to temperatures less than or equal to about 400 degrees C.

59. A thin-film transistor formed on a substrate, the thin-film transistor comprising:

a) a metallic aluminum gate disposed on the substrate,

b) an anodic aluminum oxide gate dielectric formed by anodization of the metallic aluminum gate and covering the metallic aluminum gate,

c) a channel comprising a zinc-indium oxide inorganic material disposed on at least a portion of the anodic aluminum oxide gate dielectric, and

d) a conductive source and a conductive drain of indium-tin oxide (ITO) spaced apart from each other and both disposed contiguous with the channel.

60. The thin-film transistor of claim 59, wherein the zinc-indium oxide inorganic material comprises a zinc-to-indium atomic ratio of about 1:

4.

61. The thin-film transistor of claim 59, wherein the substrate comprises a flexible material.

62. The thin-film transistor of claim 61, wherein the flexible substrate material comprises a polyimide.

63. An integrated circuit comprising the thin-film transistor of claim 59.

64. A display comprising the thin-film transistor of claim 59.

65. The thin-film transistor of claim 59, wherein each element and material thereof and their combination have the properties resulting from exposure to temperatures less than or equal to about 400 degrees C.

66. A thin-film transistor formed on a substrate, the thin-film transistor comprising:

a) conductive means for gating disposed on the substrate,

b) dielectric means for covering and insulating the conductive means for gating, the dielectric means for covering and insulating being formed by anodization of the conductive means for gating,

c) channel means for controllably conducting current carriers, the channel means for controllably conducting current carriers comprising a multi-cation-oxide inorganic material disposed on at least a portion of the dielectric means for covering and insulating, and

d) conductive source and drain means for injecting and collecting current carriers respectively, the source and drain means for injecting and collecting current carriers being spaced apart from each other and both being disposed contiguous with the channel means for controllably conducting current carriers.

67. The thin-film transistor of claim 66, wherein each element and material thereof and their combination have the properties resulting from exposure to temperatures less than or equal to about 400 degrees C.

68. A method of using a multi-cation oxide, comprising the steps of:

a) providing a substrate,

b) depositing end patterning a metal gate,

c) forming a gate dielectric on the metal gate by anodization of the metal gate,

d) depositing and patterning the multi-cation oxide inorganic material over at least a portion of the gate dielectric to form a channel layer for a thin-film transistor, and

e) depositing and patterning a conductive source and conductive drain spaced apart from each other and disposed in contact with the channel layer, whereby a thin-film transistor is fabricated.

69. A thin-film transistor formed on a substrate, the thin-film transistor comprising:

a) means for gating disposed on the substrate,

b) means for covering and insulating the means for gating, the means for covering and insulating being formed by anodization of the means for gating,

c) means for controllably conducting current carriers, comprising a multi-cation-oxide inorganic material disposed on at least a portion of the means for covering and insulating, and

d) means for injecting and means for collecting current carriers, the means for injecting and means for collecting current carriers being spaced apart from each other and both being disposed contiguous with the means for controllably conducting current carriers.

70. The thin-film transistor of claim 69, wherein each element and material thereof and their combination have the properties resulting from exposure to temperatures less than or equal to about 400 degrees C.