Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics

• US 7,427,800 B2
• Filed: 11/12/2004
• Issued: 09/23/2008
• Est. Priority Date: 02/02/2004
• Status: Expired due to Fees

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Hamza Yilmaz
• Inventors: Yilmaz, Hamza
• Primary Examiner(s): Malsawma; Lex
• Assistant Examiner(s): Kraig; William F
• Application Number:
  US10/987,761
• Publication Number:
  US 20050167744A1
• Time in Patent Office: 1,411 Days
• Field of Search: 257488-491, 257494-495, 257/E29.008, 257/E29.014, 257/E29.023, 257/29.022, 438/140
• US Class Current: 257/488
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/8605 Resistors with PN junctions
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 Å gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.

Claims

1. A trench-gated semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer formed on the substrate;

first and second trenches formed in the epitaxial layer, said first and second trenches being separated by a mesa;

a gate dielectric layer lining the walls and floor of each of the trenches;

a gate electrode in each of the trenches, the gate electrode being bounded by the gate dielectric layer;

a body region of a second conductivity type in the mesa;

a source region of the first conductivity type adjacent a wall of the trench and the top surface of the epitaxial layer;

a drift region of the epitaxial layer located below the body region and being doped with material of the first conductivity type;

a field shield region of a second conductivity type located below each of the trenches, the lateral sides of the field shield region being bounded by dielectric sidewall spacers, the dielectric sidewall spacers being interposed between the field shield region and the drift region of the epitaxial layer, the field shield region being bounded from below by a PN junction; and

a metal layer on top of the epitaxial layer and in electrical contact with the source region and the body region;

wherein the field shield region is electrically shorted to the source region and the body region.

2. The device of claim 1 wherein the dielectric sidewall spacers comprise silicon dioxide.

3. The device of claim 1 wherein the gate dielectric layer comprises silicon dioxide.

4. The device of claim 1 further comprising a body contact region of the second conductivity type adjacent a top surface of the mesa.

5. The device of claim 1 wherein the field shield region is electrically connected to the source and body regions by means of the metal layer and a well of the second conductivity type.

6. The device of claim 1 wherein said mesa is hexagonal when viewed from above, the device comprising a plurality of said hexagonal mesas.

7. The device of claim 1 wherein said mesa is square when viewed from above, the device comprising a plurality of said square mesas.

8. The device of claim 1 wherein said mesa is circular when viewed from above, the device comprising a plurality of said circular mesas.

9. The device of claim 1 wherein said mesa is in the form of a longitudinal stripe, the device comprising a plurality of said mesas arranged parallel to each other.

10. The device of claim 1 wherein said device is a MOSFET.

11. The device of claim 1 wherein said device is an insulated gate bipolar transistor.

12. A termination region in a power semiconductor device die, said device having at least two terminals, said termination region comprising a region of a first conductivity type, said termination region further comprising:

a plurality of trenches, said trenches being parallel to an edge of the die, each of said trenches having a sidewall and a floor lined with a dielectric layer, each of said trenches comprising a layer of a conductive material; and

a field shield region directly below each of said trenches, said field shield region being doped with material of a second conductivity type, said field shield region being bounded laterally by a dielectric spacer and being bounded from below by a PN junction with said region of first conductivity type;

wherein said conductive material in each trench is in direct electrical contact with the field shield region directly below said trench but there is no direct electrical connection between said conductive material in each trench and said conductive material in the other ones of said trenches or any of said terminals.

13. A device comprising:

a semiconductor body comprising a region of a first conductivity type;

a groove formed in the region of first conductivity type;

a dielectric layer lining the surfaces of the groove;

a conductive material in the groove, the conductive material being bounded by the dielectric layer; and

a field shield region of a second conductivity type located below the groove, the lateral sides of the field shield region being bounded by dielectric sidewalls, the dielectric sidewalls being interposed between the field shield region and the region of first conductivity type;

the bottom of said field shield region being bounded by PN junction between said field shield region and said region of first conductivity type;

wherein the field shield region is electrically shorted to an electrode on a top surface of the semiconductor body.

14. A device comprising:

a semiconductor body comprising a region of a first conductivity type;

a groove formed in the region of first conductivity type;

a dielectric layer lining the surfaces of the groove;

a conductive material in the groove, the conductive material being bounded by the dielectric layer;

a field shield region of a second conductivity type located below the groove, the lateral sides of the field shield region being bounded by dielectric sidewalls, the dielectric sidewalls being interposed between the field shield region and the region of first conductivity type;

the bottom of said field shield region being bounded by PN junction between said field shield region and said region of first conductivity type; and

a voltage source, the field shield region being electrically shorted to the voltage source.

15. A termination region in a power semiconductor device die, said device having at least two terminals, said termination region comprising a region of a first conductivity type, said termination region further comprising:

a plurality of trenches, said trenches being parallel to an edge of the die, each of said trenches having a sidewall and a floor lined with a dielectric layer, each of said trenches comprising a layer of a conductive material, said conductive material being insulated from the semiconductor material of the die by said dielectric layer; and

a field shield region directly below each of said trenches, said field shield region being doped with material of a second conductivity type, said field shield region being bounded laterally by a dielectric spacer and being insulated from said conductive material by said dielectric layer, the field shield region being bounded from below by a PN junction with said region of first conductivity type;

wherein there is no direct electrical connection between the conductive material in each trench and the conductive material in the other ones of said trenches or any of said terminals.