Receiver and method thereof

• US 7,427,938 B2
• Filed: 01/13/2006
• Issued: 09/23/2008
• Est. Priority Date: 01/18/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yong-Woon
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US11/331,226
• Publication Number:
  US 20060158366A1
• Time in Patent Office: 984 Days
• Field of Search: 375/344, 375/297, 375/355, 375/148, 375/222, 342/451, 341/155, 370/476
• US Class Current: 341/155
• CPC Class Codes: H04B 1/001 Channel filtering, i.e. selecting a frequency channel within the SDR system multiplexing of multicarrier modulation signals being represented by different frequencies H04L5/06; multiplexing of multicarrier modulation signals H04L5/023
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

A receiver and method thereof. The example receiver may include an analog-to-digital (ADC) converter for performing an over-sampling operation on a received signal to generate output data, the over-sampling operation based on a sampling frequency and an over-sampling coefficient and a fast fourier transform (FFT) calculating unit for performing a FFT on the output data of the ADC converter.

Claims

1. A receiver, comprising:

an analog-to-digital converter (ADC) for performing an over-sampling operation on a received signal to generate output data, the over-sampling operation based on a sampling frequency and an over-sampling coefficient, wherein the over-sampling coefficient is determined by an input unit; and

a fast Fourier transform (FFT) calculating unit for performing a FFT operation on the output data of the ADC.

2. The receiver of claim 1, wherein the received signal is an analog signal.

3. The receiver of claim 1, wherein the sampling frequency is a Nyquist sampling frequency.

4. The receiver of claim 1, wherein the receiver is included in an orthogonal frequency division multiplexing (OFDM) system.

5. The receiver of claim 1, wherein the output data is a plurality of phase-shifted versions of the received signal.

6. The receiver of claim 1, wherein the FFT calculating unit comprises:

at least one FFT calculator that performs the FFT operation on the output data; and

at least one phase compensating unit that compensates a phase variation of the output data based on the over-sampling coefficient.

7. The receiver of claim 1, wherein the ADC is a variable frequency ADC.

8. The receiver of claim 1, wherein the over-sampling coefficient is a positive integer greater than or equal to 1.

9. The receiver of claim 1, wherein the FFT calculating unit operates at a processing speed that scales with the over-sampling coefficient.

10. The receiver of claim 1, wherein a phase variation of the output data is a phase difference, in a frequency domain, based on a time delay of the output data.

11. The receiver of claim 6, further comprising:

a mixer that mixes phase compensated data sequences received from at least one phase compensating unit and outputs a data sequence based on the mixed phase compensated data sequences.

12. The receiver of claim 1, wherein the output data of the ADC is configured with data blocks that are equal in number to the over-sampling coefficient, and

wherein each of the data blocks is arranged in parallel and separated by a time interval based on the sampling frequency.

13. The receiver of claim 1, wherein the FET calculating unit includes a plurality of lower-speed FFT calculators, and

wherein each of the plurality of lower-speed FFT calculators receives a portion of the output data from the ADC and performs a FFT operation on the received portion.

14. The receiver of claim 13, wherein a number of lower-speed FFT calculators equals the over-sampling coefficient.

15. The receiver of claim 13, wherein the FFT operations are performed by the plurality of lower-speed FFT calculators concurrently on each of the received portions of the output data.

16. The receiver of claim 1, wherein the FFT calculating unit comprises a higher-speed FFT calculator, and

wherein the higher-speed FFT calculator receives the output data from the ADC and performs a EFT operation on a received portion of the output data.

17. The receiver of claim 16, wherein the higher-speed FFT calculator is the only FFT calculator in the FFT calculating unit, and

wherein the higher-speed FFT calculator serially processes received portions of the output data.

24. A method of receiving data with the receiver of claim 1.

18. A method for receiving data, comprising:

determining an over-sampling coefficient;

over-sampling a received signal based on the over-sampling coefficient and a sampling frequency to generate over-sampled data; and

performing a fast Fourier transform (FFT) operation on the over-sampled data to generate FFT over-sampled data.

19. The method of claim 18, further comprising:

compensating for phase shifts in the EFT over-sampled data based on the over-sampling coefficient; and

combining the compensated FFT over-sampled data to generate an output signal.

20. The method of claim 19, wherein the output signal is a demodulated signal with an improved signal-to-noise (SNR) ratio.

21. The method of claim 18, wherein the over-sampling coefficient is a positive integer greater than or equal to 1.

22. The method of claim 18, wherein the EFT operation is performed at a processing speed that scales with the over-sampling coefficient.

23. The method of claim 18, wherein performing the FFT operation generates phase shifts in the FFT over-sampled data.