Semiconductor memory device sharing a data line sense amplifier and a write driver in order to reduce a chip size

• US 7,428,168 B2
• Filed: 06/30/2006
• Issued: 09/23/2008
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Seung-Lo
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/478,527
• Publication Number:
  US 20070070697A1
• Time in Patent Office: 816 Days
• Field of Search: 365/185.13, 365/230.03, 365/185.23
• US Class Current: 365/185.13
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A semiconductor memory device includes a first and a second bank, a global data line, a first and a second data line, a data transmitter, and a switch. The global data line is configured between the first and the second banks and commonly shared by the first and the second banks. The first and the second local data lines are respectively configured in the first and the second banks. The data transmitter is configured to transmit data between the global data line and the first and the second local data lines. The switch is configured to couple the data transmitter with the first or the second local data line in response to a corresponding bank selection signal.

Claims

1. A semiconductor memory device, comprising:

a first and a second bank;

a global data line configured between the first and the second banks and commonly shared by the first and the second banks, wherein the global data line is commonly used by input data and output data;

a first local data line configured in the first bank;

a second local data line configured in the second bank;

a data transmitter configured to transmit data between the global data line and the first and the second local data lines; and

a switch configured to couple the data transmitter with the first or the second local data line in response to a corresponding bank selection signal.

2. The semiconductor memory device as recited in claim 1, wherein the data transmitter includes:

a write driver configured to transmit data loaded at the global data line to one of the first and the second local data lines; and

a data line sense amplifier configured to transmit data loaded at one of the first and the second local data lines to the global data line.

3. The semiconductor memory device as recited in claim 2, wherein the switch includes:

a first switch configured to connect the first local data line with the data transmitter in response to a first bank selection signal; and

a second switch configured to connect the second local data line with the data transmitter in response to a second bank selection signal.

4. The semiconductor memory device as recited in claim 3, wherein the first and the second switches comprise NMOS transistors.

5. A semiconductor memory device, comprising:

a plurality of banks; and

a plurality of global data lines commonly shared by the plurality of banks, wherein each global data line is commonly used by input data and output data; and

a plurality of data transmitters, each of which is commonly shared by two adjacent said banks to transmit data between the global data and the two adjacent banks,

wherein each bank includes;

a plurality of local data lines; and

a plurality of switches corresponding to the local data lines configured to selectively couple corresponding data transmitters with corresponding local data lines in response to a corresponding bank selection signal.

6. The semiconductor memory device as recited in claim 5, wherein each data transmitter includes:

a write driver configured to transmit data loaded at the global data line to one of corresponding local data lines included in the corresponding two adjacent banks; and

a data line sense amplifier configured to transmit data loaded at one of the corresponding local data lines included in the corresponding two adjacent banks to the global data line.

7. The semiconductor memory device as recited in claim 6, wherein each switch comprises an NMOS transistor.