Method of fabricating strain-silicon CMOS

• US 7,429,775 B1
• Filed: 03/31/2005
• Issued: 09/30/2008
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Nayak, Deepak Kumar, Luo, Yuhao
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): Tran; Tan N
• Application Number:
  US11/095,814
• Time in Patent Office: 1,279 Days
• Field of Search: 257/369, 257/374, 257/E29.193, 257/288, 257/341, 257/350, 257/351, 257/401
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Recesses are formed in the drain and source regions of an MOS transistor. The recesses are formed using two anisotropic etch processes and first and second sidewall spacers. The recesses are made up of first and second recesses, and the depths of the first and second recesses are independently controllable. The recesses are filled with a stressed material to induce strain in the channel, thereby improving carrier mobility. The widths and depths of the first and second recesses are selectable to optimize strain in the channel region.

Claims

1. A metal-oxide-semiconductor (“

MOS”

) transistor comprising;

a channel region;

a source region;

a drain region;

stressed material in at least one of the source region and the drain region having a first edge and a second edge along one end of the stressed material, the first edge being between the second edge and the channel region so as to induce strain in the channel region sufficient to increase carrier mobility in the channel region; and

a source/drain extension region between the first edge and the channel region.

2. The MOS transistor of claim 1 wherein the stressed material comprises epitaxially grown material.

3. The MOS transistor of claim 1 wherein the stressed material comprises selective epitaxial growth SiGe.

4. The MOS transistor of claim 1 wherein the stressed material is disposed on semiconductor material, the stressed material including a dopant so as to provide a dopant source for the semiconductor material.

5. The MOS transistor of claim 1 wherein the stressed material comprises boron-doped SiGe.

6. The MOS transistor of claim 1 wherein the MOS transistor is a first MOS transistor in a complementary MOS (“

CMOS”

) cell.

7. The MOS transistor of claim 1 further comprising an isolation structure, wherein the first edge extends a first distance between the isolation structure and the channel region so as to provide a first selected stress producing a first strain in the channel region and the second edge extends a second selected distance between the isolation structure and the channel region so as to provide a second selected stress producing a second strain in the channel region.

8. The MOS transistor of claim 1 further comprising a source/drain extension region, wherein the first edge is next to the source/drain extension region and the second edge is next to the source/drain extension region.

9. The MOS transistor of claim 1 wherein the MOS transistor is a first MOS transistor in a complementary MOS (“

CMOS”

) cell.

10. A metal-oxide-semiconductor (“

MOS”

) transistor comprising;

a channel region;

a source region;

a drain region;

stressed material in at least one of the source region and the drain region having a first edge and a second edge along one end of the stressed material, the first edge being between the second edge and the channel region so as to induce strain in the channel region sufficient to increase carrier mobility in the channel region; and

an isolation structure, wherein the first edge extends a first distance between the isolation structure and the channel region so as to provide a first selected stress producing a first strain in the channel region and the second edge extends a second selected distance between the isolation structure and the channel region so as to provide a second selected stress producing a second strain in the channel region.

11. The MOS transistor of claim 10 wherein the stressed material comprises at least one material selected from the group consisting of epitaxially grown material, selective epitaxial growth SiGe, and boron-doped SiGe.

12. The MOS transistor of claim 10 wherein the stressed material is disposed on semiconductor material, the stressed material including a dopant so as to provide a dopant source for the semiconductor material.

13. The MOS transistor of claim 10 wherein the MOS transistor is a first MOS transistor in a complementary MOS (“

CMOS”

) cell.

14. The MOS transistor of claim 10 further comprising a source/drain extension region, wherein the first edge is next to the source/drain extension region and the second edge is next to the source/drain extension region.

15. A metal-oxide-semiconductor (“

MOS”

) transistor comprising;

a channel region;

a source region;

a drain region;

stressed material in at least one of the source region and the drain region having a first edge and a second edge along one end of the stressed material, the first edge being between the second edge and the channel region so as to induce strain in the channel region sufficient to increase carrier mobility in the channel region; and

a source/drain extension region, wherein the first edge is next to the source/drain extension region and the second edge is next to the source/drain extension region.

16. The MOS transistor of claim 15 wherein the stressed material comprises at least one material selected from the group consisting of epitaxially grown material, selective epitaxial growth SiGe, and boron-doped SiGe.

17. The MOS transistor of claim 15 wherein the stressed material is disposed on semiconductor material, the stressed material including a dopant so as to provide a dopant source for the semiconductor material.