AC-DC input buffer

• US 7,429,882 B2
• Filed: 06/08/2006
• Issued: 09/30/2008
• Est. Priority Date: 06/08/2006
• Status: Expired due to Fees

• Current Assignee: Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Original Assignee: Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Inventors: Peterson, Luverne R.
• Primary Examiner(s): Wells; Kenneth B.
• Application Number:
  US11/449,325
• Publication Number:
  US 20070285134A1
• Time in Patent Office: 845 Days
• Field of Search: 327/108, 330/260
• US Class Current: 327/108
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

An inverting input buffer that uses the best features of an AC input buffer (low delay, high speed, high input voltage swing range) and a DC input buffer (stability, reliability, ‘automatic’ high and low data setup, input VIL and VIH “Voltage Input Low” and “Voltage Input High” margins). The delay though the buffer with a nominal load is very small. Optionally, a voltage tolerant input circuit is coupled to the DC input, which enables the DC input buffer to tolerate higher voltage swings, thus allowing a single buffer to switch both high (e.g. 2.5 volts-5 volts in a 1.2 volt system) and low input voltages (e.g. below 2.5 volts in a 1.2 volt system).

Claims

1. A circuit, comprising:

a capacitance element having an input and an output;

a direct current input buffer having an input and an output, wherein the input of the direct current input buffer is coupled to the input of the capacitance element and the output of the direct current input buffer is coupled to the output of the capacitance element;

a feedback circuit coupled to the direct current input buffer, the feedback circuit is operable to change the output of the direct current output buffer to match the input of the direct current input buffer responsive to determining the output of the direct current input buffer does not match the input of the direct current input buffer;

a delay circuit coupled to the feedback circuit, the delay circuit is configured to turn off the feedback circuit a predetermined amount of time after the output of the direct current input buffer is changed to match the input of the direct current input buffer; and

an output buffer coupled to the output of the direct current input buffer and the output of the capacitance element.

2. The circuit according to claim 1, wherein the capacitance element comprises a metal capacitor having interdigitated metal lines.

3. The circuit according to claim 1, further comprising a voltage tolerant input circuit coupled in series with the input of the direct current input buffer, wherein the voltage tolerant input circuit limits the amount of voltage applied to the input of the direct current input buffer.

4. The circuit according to claim 3, wherein the voltage tolerant input circuit comprises at least one diode coupled between an input of the voltage tolerant input circuit and a supply voltage, and the at least one diode is configured to conduct if the voltage at the input of the voltage tolerant input circuit exceeds the power supply voltage by a predetermined amount.

5. The circuit according to claim 1, further comprising a voltage overprotect circuit coupled to the output of the direct current input buffer and the output of the capacitance element, the voltage overprotect circuit configured to prevent the voltage at the output of the direct current input buffer and the output of the capacitance element from exceeding an upper predetermined voltage.

6. The circuit according to claim 5, wherein the voltage overprotect circuit is further configured to prevent the voltage at the output of the direct current input buffer and the output of the capacitance element from going below a lower predetermined voltage.

7. The circuit according to claim 1, further comprising a latch coupled to the output of the direct current input buffer and the output of the capacitance element.

8. The circuit according to claim 1, wherein the output buffer is an inverting buffer.

9. A circuit, comprising:

inverting means;

means for capacitively coupling an input signal to the inverter means;

means for direct current buffering the input signal to the inverter means in parallel with the means for capacitively coupling, the means for direct current buffering having an input and an output;

means for providing feedback to the means for direct current buffering, the means for providing feedback is operable to provide feedback to the means for direct current buffering responsive to the output of the means for providing feedback not matching the input of the means for direct current buffering; and

delay means for turning off the means for providing feedback a predetermined amount of time after the output of the means for direct current buffering has been changed to match the input of the means for direct current buffering.

10. The circuit according to claim 9, further comprising means for reducing the level of the input signal to the means for direct current buffering.

11. The circuit according to claim 10, wherein the means for reducing the level of the input signal is coupled in series with the means for direct current buffering.

12. The circuit according to claim 9, further comprising means for protecting against an overvoltage coupled between the means for capacitively coupling and the inverter means.

13. The circuit according to claim 9, further comprising means for protecting against an undervoltage coupled between the means for capacitively coupling and the inverter means.

14. The circuit according to claim 9, further comprising means for latching coupled between the means for capacitively coupling and the inverter means.

15. A method, comprising:

applying a signal to an input of a buffer through a capacitance element; and

applying the signal to the input of the buffer through a direct current (DC) buffer coupled in parallel with the capacitance element concurrently to applying the signal to the capacitance element;

applying a feedback signal to the DC buffer responsive to determining an output of the DC buffer does not match the signal at the input of the DC buffer; and

turning off the feedback signal a predetermined amount of time after applying the feedback signal.

16. A method according to claim 15, further comprising latching the input of the buffer.

17. A method according to claim 15, further comprising reducing the signal level before applying the signal to the DC buffer.