Method and bit stream decoding unit using majority voting

• US 7,430,261 B2
• Filed: 07/07/2003
• Issued: 09/30/2008
• Est. Priority Date: 04/16/2002
• Status: Active Grant

• Current Assignee: Volkswagen AG
• Original Assignee: Bayerische Motoren Werke AG, General Motors Corporation (General Motors Company), Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.), DaimlerChrysler AG (Mercedes-Benz Group AG), Motorola, Inc. (Motorola Solutions, Inc.), Robert Bosch GmbH
• Inventors: Hartwich, Florian, Temple, Christopher, Hugel, Robert, Lohrmann, Peter, Müller, Bernd, Berwanger, Josef, Belschner, Ralf, Schedl, Anton, Hedenetz, Bernd, Ungermann, Jörn, Zinke, Manfred, Fuhrmann, Peter, Ebner, Christian, Elend, Bernd, Millsap, Arnold, Führer, Thomas, Forest, Thomas, Bogenberger, Florian, Rausch, Mathias, Weiler, Harald, Wuerz, Thomas, Peller, Martin, Heuts, Patrick, Eisele, Harald, Kühlewein, Matthias
• Primary Examiner(s): Payne; David C.
• Assistant Examiner(s): Bolourchi; Nader
• Application Number:
  US10/613,039
• Publication Number:
  US 20040090962A1
• Time in Patent Office: 1,912 Days
• Field of Search: 375/364, 370/392, 370/442
• US Class Current: 375/364
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/43 Majority logic or threshold decoding
• CPC Class Codes: H04J 3/0652 Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP] bus network with centralized control in which slots are of a TDMA packet structure H04L12/4035
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04J 3/0694 Synchronisation in a TDMA node, e.g. TTP
• CPC Class Codes: H04L 12/40026 Details regarding a bus guardian
• CPC Class Codes: H04L 12/4035 in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit TDM/TDMA multiplex systems per se H04J3/1694; hybrid switching systems H04L12/64
• CPC Class Codes: H04L 12/417 with deterministic access, e.g. token passing
• CPC Class Codes: H04L 12/44 Star or tree networks
• CPC Class Codes: H04L 12/6418 Hybrid transport
• CPC Class Codes: H04L 2012/40241 Flexray
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle
• CPC Class Codes: H04L 2012/6435 Bus
• CPC Class Codes: H04L 2012/644 Star
• CPC Class Codes: H04L 2012/6459 Multiplexing, e.g. TDMA, CDMA
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 43/0847 Transmission error
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A method and a bit stream decoding unit for bit stream decoding has a bit stream comprising a number of consecutive samples. In order to provide for rapid and, in particular, reliable decoding of the bit stream, a detection window comprising a number of samples is defined and the detection window is positioned at certain positions on the bit stream in order to comprise certain samples with respective sample values. A majority voting is applied to the sample values in the detection window and, in dependence on the result of the majority voting, the bit stream is decoded and respective bit values are generated.

Claims

1. A method for bit stream decoding of a received bit stream, the method comprising the steps of:

a) defining a detection window of sample values which are used to determine a value of a bit cell in a bit stream;

b) applying a majority voting to said sample values within said detection window;

c) generating a value of said bit cell in dependence on the results of step b); and

d) decoding the bit stream using the bit cell values generated in step c), wherein said detection window is positioned at an expected edge between two bit cells of the bit stream to overlap at least one sample of a first bit cell and at least one sample of a subsequent bit cell, having respective sample values, in order to perform bit edge detection.

2. The method of claim 1, wherein said detection window comprises an odd number of samples.

3. The method of claim 1, wherein said detection window is centered on an expected center of a bit cell of the bit stream to only overlap samples of said bit cell for detecting a bit value of said bit cell.

4. The method of claim 3, wherein glitches or spikes in the bit stream are filtering out.

5. The method of claim 1, including:

sampling said bit cell in the received bit stream, to generate at least two sample values of said bit cell.

6. A method for bit stream decoding of a received bit stream, the method for comprising the steps of:

a) defining a detection window of sample values which are used to determine a value of a bit cell in a bit stream;

b) applying a majority voting to said sample values within said detection window;

c) generating a value of said sampled bit cell in dependence on the results of step b); and

d) decoding the bit stream using the bit values generated in step c), wherein said detection window is positioned on an expected center of said bit cell of the bit stream in dependence on a predetermined offset-parameter and in dependence on a predetermined parameter specifying a number of samples in said detection window to only overlap samples of said bit cell for detecting a bit value of said bit cell.

7. The method of claim 6, wherein said detection window comprises an odd number of samples.

8. The method of claim 6, wherein said detection window is centered on an expected center of a bit cell of the bit stream to only overlap samples of said bit cell for detecting a bit value of said bit cell.

9. The method of claim 7, wherein glitches or spikes in the bit stream are filtering out.

19. The method of claim 6, including:

sampling said bit cell in the received bit stream, to generate at least two sample values of said bit cell.

10. A device for decoding a received bit stream, the device comprising:

means for defining a detection window of sample values which are used to determine a value of a bit cell in a bit stream;

means for applying majority voting to said sample values within said detection window;

means for generating a value of said sampled bit cell in dependence on results of said voting; and

means for decoding the bit steam using the generated bit cell values, wherein said detection window is positioned at an expected edge between two bit cells of the bit stream according to a predetermined offset-parameter and according to a predetermined parameter specifying a number of samples in said detection window to only overlap samples of said bit cell for detecting a bit value of said bit cell.

17. The device of claim 10, wherein said detection window is positioned at an expected edge between two bit cells of the bit stream to only overlap samples of said bit cell for detecting a bit value of said bit cell.

18. The device of claim 17, wherein said detection window comprises an odd number of samples.

20. The device of claim 10, wherein glitches or spikes in the bit stream are filtering out.

21. The device of claim 17, including a sampling unit for sampling said bit cell in the received bit stream to generate at least two sample values of said bit cell.

22. A node in a communication system, including a device as claimed in claim 17.

11. A device for decoding a received bit stream, the device comprising:

means for defining a detection window of sample values which are used to determine a value of a bit cell in a bit stream;

means for applying majority voting to said sample values within said detection window;

means for generating a value of said sampled bit cell in dependence on results of said voting; and

means for decoding the bit steam using the generated bit cell values, wherein said detection window is positioned at an expected edge between two bit cells of the bit stream to overlap at least one sample of a first bit cell and at least one sample of a subsequent bit cell, having respective sample values, in order to perform bit edge detection.

12. The device of claim 11, wherein said detection window comprises an odd number of samples.

13. The device of claim 11, wherein said detection window is centered on an expected edge between two bit cells of the bit stream to only overlap samples of said bit cell for detecting a bit value of said bit cell.

14. The device of claim 13, wherein glitches or spikes in the bit stream are filtering out.

15. A node in a communication system, the node comprising the device of claim 11.

16. The device of claim 11, including a sampling unit for sampling said bit cell in the received bit stream to generate at least two sample values of said bit cell.

23. A computer readable medium having instructions executable by at least one of a computer and a microprocessor stored thereon for performing the steps of:

a) defining a detection window of sample values which are used to determine a value of a bit cell in a bit stream;

b) applying a majority voting to said sample values within said detection window;

c) generating a value of said bit cell in dependence on the results of step b); and

d) decoding the bit stream using the bit cell values generated in step c), wherein said detection window is positioned at an expected edge between two bit cells of the bit stream to overlap at least one sample of a first bit cell and at least one sample of a subsequent bit cell, having respective sample values, in order to perform bit edge detection.